Application specific integrated circuit accelerators
AssigneeGoogle Inc.
InventorsMichial Allen Gunter, Charles Henry Leichner, IV, Tammo Spalink
Life of this patent
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Abstract
A tile including circuitry for use with machine learning models, the tile including: a first computational array of cells, in which the computational array of cells is a sub-array of a larger second computational array of cells; local memory coupled to the first computational array of cells; and multiple controllable bus lines, in which a first subset of the multiple controllable bus lines include multiple general purpose controllable bus lines couplable to the local memory.
Claims12
An apparatus for use with machine learning models, the apparatus comprising:
- an arithmetic computational circuit, wherein the arithmetic computational circuit comprises a first array of cells configured to perform mathematical operations;
- memory;
- a plurality of switchable bus lines comprising a first switchable bus line subset and a second switchable bus line subset,
- wherein the first switchable bus line subset is configured to control whether data is transferred between the first switchable bus line subset and the memory along a first dimension and whether data is transferred between the first switchable bus line subset and the arithmetic computational circuit along the first dimension,
- wherein the second switchable bus line subset is configured to control whether data is transferred along a second dimension that is orthogonal to the first dimension,
- wherein the first switchable bus line subset comprises at least one control element positioned proximate to a first memory circuit of the memory and to the first array of cells, wherein the at least one control element of the first switchable bus line subset is configured to control whether data is transferred between the first switchable bus line subset and the first memory circuit and whether data is transferred between the first switchable bus line subset and the first array of cells.
An apparatus for use with machine learning models, the apparatus comprising:
- an arithmetic computational circuit, wherein the arithmetic computational circuit comprises a first array of cells configured to perform mathematical operations;
- memory;
- a plurality of switchable bus lines comprising a first switchable bus line subset and a second switchable bus line subset,
- wherein the first switchable bus line subset is configured to control whether data is transferred between the first switchable bus line subset and the memory along a first dimension and whether data is transferred between the first switchable bus line subset and the arithmetic computational circuit along the first dimension,
- wherein the second switchable bus line subset is configured to control whether data is transferred along a second dimension that is orthogonal to the first dimension;
- and
- a vector processing unit, wherein a first half of the first array of cells is arranged on a first side of the vector processing unit, and wherein a second half of the first array of cells is arranged on a second side of the vector processing unit that is opposite to the first side of the vector processing unit.
Dependencies are inferred from the claim text.