Match-slave latch with skewed clock

A method of generating master clock signals and slave clock signals for controlling a flip-flop having a master latch and a slave latch, the method comprising:

• receiving, by a skewed clock circuit, a clock signal;
• generating, by the skewed clock circuit, at least two master clock signals and at least two slave clock signals, wherein the at least two master clock signals and the at least two slave clock signals are different clock signals, wherein the at least two master clock signals include a master clock signal and an inverted master clock signal that is an inverted version of the master clock signal and wherein the at least two slave clock signals include a slave clock signal and an inverted slave clock signal that is an inverted version of the slave clock signal;
• providing the at least two master clock signals to the master latch and the at least two slave clock signals to the slave latch;
• and
• controlling transmission gates of the master latch with the at least two master clock signals and the slave latch with the at least two slave clock signals;
• wherein the skewed clock circuit comprises both of a NOR gate and a NAND gate,
• wherein the NOR gate generates (i) the master clock signal as logic high when the clock signal and the inverted version of the slave clock signal are both logic low, and (ii) the master clock signal as logic low when one or more of the clock signal and the inverted version of the slave clock signal is logic high, and
• wherein the NAND gate generates (a) the slave clock signal as logic low when the clock signal and the inverted version of the slave clock signal are both logic high, and (b) the slave clock signal as logic high when one or more of the clock signal and the inverted version of the slave clock signal is logic low.

A device comprising:

• a data flip-flop comprising a plurality of latches;
• and
• a clock circuit coupled to the data flip-flop and comprising both of a NOR gate and a NAND gate, the clock circuit configured to receive a clock signal and generate a plurality of clock signals, each of the plurality of clock signals are different from each other, wherein the plurality of clock signals comprises at least two master clock signals including a master clock signal and an inverted master clock signal that is an inverted version of the master clock signal and at least two slave clock signals including a slave clock signal and an inverted slave clock signal that is an inverted version of the slave clock signal, wherein the at least two master clock signals and the at least two slave clock signals are provided to the plurality of latches;
• wherein the NOR gate generates (i) the master clock signal as logic high when the clock signal and the inverted version of the slave clock signal are both logic low, and (ii) the master clock signal as logic low when one or more of the clock signal and the inverted version of the slave clock signal is logic high, and
• wherein the NAND gate generates (a) the slave clock signal as logic low when the clock signal and the inverted version of the slave clock signal are both logic high, and (b) the slave clock signal as logic high when one or more of the clock signal and the inverted version of the slave clock signal is logic low.