Low power high precision piecewise linear (PWL) waveform generator

A method for generating a piece-wise linear (PWL) waveform, comprising:

• generating a reference current;
• charging and discharging an output capacitor, based on the reference current, to develop an output voltage to form a piece-wise linear (PWL) waveform;
• using a clock-controlled switch network connected to the current sources and to the output capacitor to control the charging/discharging of the output capacitor;
• and
• using a feedback control loop to sense the output voltage and to control the current generator to vary the reference current based on the output voltage,
• wherein the feedback control loop comprises differential and common mode feedback paths to regulate a differential output voltage and a common mode output voltage.

An auxiliary capacitor path for use in a current steering circuit having a current source that drives a load impedance, comprising:

• a first switch controlled by a first clock signal to periodically connect and disconnect an output of the current source to and from the load impedance;
• a capacitor;
• a second switch controlled by a second clock signal to periodically connect and disconnect the capacitor to and from the output of the current source while the current source is respectively disconnected from and connected to the load impedance;
• and
• wherein the capacitor has a capacitance C=I*T/V, wherein:
• I is a predetermined current generated by the current source;
• T is a time during which the second switch connects the capacitor to the output of the current source according to the second clock signal;
• and
• V is a predetermined voltage to which the capacitor is charged by the current source to mitigate glitching of a voltage across the load impedance when the first switch connects the output of the current source to the load impedance according to the first clock signal.

A method for use in a current steering circuit having a current source that drives a load impedance, comprising:

• periodically connecting and disconnecting an output of the current source to and from the load impedance using a first switch controlled by a first clock signal;
• periodically connecting and disconnecting an auxiliary capacitor to and from the output of the current source, using a second switch controlled by a second clock signal, while the current source is respectively disconnected from and connected to the load impedance;
• and
• wherein the auxiliary capacitor has a capacitance C=I*T/V, wherein:
• I is a predetermined current generated by the current source;
• T is a time during which the second switch connects the auxiliary capacitor to the output of the current source according to the second clock signal;
• and
• V is a predetermined voltage to which the auxiliary capacitor is charged by the current source to mitigate glitching of a voltage across the load impedance when the first switch connects the output of the current source to the load impedance according to the first clock signal.