Pulse train conditioning circuits and related methods

An apparatus comprising:

• a first transistor having a first current terminal and a first gate terminal;
• a second transistor having a second current terminal and a second gate terminal, the second gate terminal coupled to the first gate terminal;
• a third transistor having a third current terminal and a third gate terminal, the third gate terminal coupled to the first gate terminal and the second gate terminal;
• and
• a first switch coupled to the first current terminal, the second current terminal, and the third current terminal, the first switch configured to couple the third current terminal to the first current terminal or the second current terminal based on a code to adjust a ratio of a first quantity of one or more transistors over a second quantity of one or more transistors, the first quantity including at least the first transistor, the second quantity including at least the second transistor.

A system comprising:

• a power converter;
• a gate driver coupled to the power converter, the gate driver including:
• a trim circuit;
• and
• delay logic coupled to the trim circuit, the delay logic including:
• first transistors;
• a second transistor coupled to the first transistors;
• a third transistor coupled to the second transistor;
• switches, each of the switches coupled to a respective one of the first transistors, the switches to couple a set of the first transistors to a current terminal of the third transistor;
• a capacitor;
• and
• a fourth transistor coupled to the capacitor and the third transistor, the fourth transistor to discharge the capacitor by facilitating a current to flow from the capacitor through the set of the first transistors, the third transistor, and the fourth transistor.