Digital correlated double sampling circuit and image sensor including the same

A digital correlated double sampling (CDS) circuit comprising:

• a first latch circuit configured to store first reset component data by latching a first count signal based on a first comparison signal during a reset interval and configured to store first image component data by latching the first count signal based on a second comparison signal during an image interval;
• a second latch circuit configured to store second reset component data by latching a second count signal based on the first comparison signal during the reset interval and configured to store second image component data by latching the second count signal based on the second comparison signal during the image interval, the second count signal being obtained by delaying the first count signal by a first delay amount;
• a decision circuit configured to output a decision signal based on an interval direction signal during the reset interval and configured to output the decision signal based on the interval direction signal and identity of the first image component data and the second image component data;
• a switch circuit, connected to the first latch circuit and the second latch circuit, configured to output the second reset component data during the reset interval and configured to output one of the first image component data and the second image component data as a selected image component data during the image interval;
• and
• a calculating circuit, connected to the switch circuit, configured to generate effective image data by subtracting the second reset component data from the selected image component data and configured to sequentially output the effective image data, wherein the interval direction signal designates one of the reset interval and the image interval.

An image sensor comprising:

• a pixel array configured to generate a plurality of analog pixel signals based on incident light;
• a comparison block configured to generate a plurality of first comparison signals and a plurality of second comparison signals by comparing the plurality of analog pixel signals with a ramp signal;
• a global counter configured to generate a count signal based on a counter clock signal;
• and
• a digital correlated double sampling (CDS) block configured to generate a plurality of effective image data corresponding to the plurality of analog pixel signals by performing a digital CDS based on the plurality of first comparison signals, the plurality of second comparison signals and the count signal, wherein:
• the comparison block includes a plurality of comparators, each comparator receives a respective one of the plurality of analog pixel signals, the digital CDS block includes a plurality of digital CDS circuits, and each digital CDS circuit is connected to a respective one of the plurality of comparators, and
• each digital CDS circuit includes:
• a first latch circuit configured to store first reset component data by latching the count signal based on a respective one of the plurality of first comparison signals during a reset interval;
• a second latch circuit configured to store second reset component data by latching the count signal based on a reset comparison signal during the reset interval and configured to store image component data by latching the count signal based on a selected comparison signal during an image interval, the selected comparison signal being selected from a first image comparison signal and a second image comparison signal, the first image comparison signal and the second image comparison signal being obtained by delaying a respective one of the plurality of second comparison signals;
• a decision circuit configured to output a decision signal by determining bit-wise identity of the first reset component data and the second reset component data;
• a delay control circuit configured to output the reset comparison signal by delaying the first comparison signal based on an interval direction signal indicating one of the reset interval and the image interval during the reset interval, and configured to output one of the first image comparison signal and the second comparison signal as the selected comparison signal based on the interval direction signal and the decision signal during the image interval;
• and
• a calculating circuit configured to generate effective image data by subtracting the second reset component data from the image component data and configured to sequentially output the effective image data.