Field bus system with a switchable slew rate

A method comprising:

• producing a bus voltage between a first bus line and a second bus line on the basis of a logic signal, wherein the bus voltage is changed at a settable slew rate;
• receiving, from a receiver circuit coupled to the first bus line and the second bus line, a second logic signal which represents a current level of the bus voltage;
• detecting, on the basis of the second logic signal, when an arbitration phase ends and a data transmission phase begins according to a bus protocol;
• and
• setting the slew rate, wherein a higher slew rate is set during at least an arbitration field of the arbitration phase of a data frame contained in the first logic signal than during the data transmission phase of the data frame, wherein the data transmission phase of the data frame occurs after the arbitration phase.

A circuit comprising:

• an output stage which is connected to a first bus line and to a second bus line;
• a transmission buffer which is designed to receive a first data signal and to provide a first logic signal which represents the first data signal;
• a driver circuit which is designed to control the output stage on the basis of the first logic signal in such a manner that a corresponding bus voltage is produced between the first bus line and the second bus line;
• a slew-rate controller which is coupled to the driver circuit and is designed to set a slew rate of the driver circuit on the basis of an input signal;
• a monitoring circuit which is designed to generate the input signal for the slew-rate controller, wherein the input signal indicates a higher slew rate during an arbitration phase of a data frame contained in the first logic signal than during a data transmission phase of the data frame;
• a receiver circuit which is coupled to the first bus line and to the second bus line in order to receive the bus voltage and is designed to generate a second logic signal which represents a current level of the bus voltage;
• a reception buffer which is designed to output a second data signal which represents the second logic signal;
• and
• wherein the monitoring circuit has a protocol handler, to which the second logic signal is supplied and which is designed to detect, on the basis of the second logic signal, when the arbitration phase ends and the data transmission phase begins according to a bus protocol.