Ultra-low latency advanced encryption standard
AssigneeIntel Corporation
InventorMichael Kounavis
Life of this patent
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Abstract
In one example, an apparatus for Advanced Encryption Standard (AES) substitutions box (S-box) encryption includes an S-Box logic function and a MixColumns multiplication operation. The S-box logic function takes as input a state and is an 8-bit to 8-bit logic function, and wherein the S-box logic function is minimized such that an S-box round comprises nine not-and (NAND) levels and duplications of a logical product of the minimized S-box logic function are eliminated. The MixColumns multiplication operation comprises a plurality of factors that are exclusive ORed (XOR) with an output of the S-box round to obtain a scaled 16-byte output.
Claims9
A method to enable an Advanced Encryption Standard (AES) substitution box (S-box), comprising:
- finding, via AES circuitry, prime implicants of an S-box logic function;
- determining, via the AES circuitry, essential implicants from the prime implicants of the S-box function;
- minimizing, via the AES circuitry, the essential implicants and finding selected implicants;
- removing, via the AES circuitry, duplications from the essential implicants and the selected implicants to obtain final implicants;
- expressing, via the AES circuitry, the S-box logic function as the final implicants;
- and
- scaling, via the AES circuitry, the S-box logic function expressed as final implicants by factors from a MixColumns multiplication operation, wherein the S-box logic function and the MixColumns multiplication operation comprise nine NAND levels and five XOR levels.
Dependencies are inferred from the claim text.