Phasing detection of asynchronous dividers

A clock and data recovery (CDR) system comprising:

• a first divider configured to output a first divided clock signal;
• a second divider configured to output a second divided clock signal;
• and
• an asynchronous clock phasing detection circuit comprising:
• a comparison circuit configured to process the first divided clock signal and the second divided clock signal to generate an output signal indicating when the first divided clock signal and the second divided clock signal are in different states;
• an oscillator configured to output a control clock signal;
• a first counter controlled by the control clock signal and configured to count the output signal;
• and
• a control circuit configured to process a first count signal from the first counter to generate a detection signal indicating a relative phasing between the first divided clock signal and the second divided clock signal, wherein the control circuit is configured to control the oscillator to set an oscillation frequency of the control clock signal.

A method of asynchronous clock phasing detection, the method comprising:

• dividing a first clock signal to generate a first divided clock signal using a first divider;
• dividing a second clock signal to generate a second divided clock signal using a second divider;
• generating an output signal indicating when the first divided clock signal and the second divided clock signal are in different states;
• generating a first count signal by counting the output signal based on timing of a control clock signal using a first counter;
• generating a detection signal indicating a relative phasing between the first divided clock signal and the second divided clock signal based on the first count signal;
• generating a second count signal by counting a number of cycles of the control clock signal, and
• generating the detection signal based on ratio of the first count signal and the second count signal.

A method of asynchronous clock phasing detection, the method comprising:

• dividing a first clock signal to generate a first divided clock signal using a first divider;
• dividing a second clock signal to generate a second divided clock signal using a second divider;
• genera tin output signal indicating when the first divided clock signal and the second divided clock signal are in different states;
• generating a first count signal by counting the output signal based on timing of a control clock signal using a first counter;
• generating a detection signal indicating a relative phasing between the first divided clock signal and the second divided clock signal based on the first count signal;
• and
• controlling a state of at least one of the first divider or the second divider based on the detection signal.

An asynchronous clock phasing detection circuit comprising:

• a comparison circuit configured to process a first divided clock signal and a second divided clock signal to generate an output signal indicating when the first divided clock signal and the second divided clock signal are in different states;
• an oscillator configured to output a control clock signal;
• a first counter controlled by the control clock signal and configured to count the output signal;
• a control circuit configured to process a first count signal from the first counter to generate a detection signal indicating a relative phasing between the first divided clock signal and the second divided clock signal;
• and
• a second counter configured to count a number of cycles of the control clock signal, the control circuit further configured to generate the detection signal based on ratio of the first count signal from the first counter and a second count signal from the second counter.