Spike generation circuit, information processing circuit, power conversion circuit, detector, and electronic circuit

A spike generation circuit comprising:

• a first CMOS inverter connected between a first power supply and a second power supply, an output node of the first CMOS inverter being coupled to a first node;
• a first switch connected in series with the first CMOS inverter, between the first power supply and the second power supply;
• an inverting circuit that outputs an inversion signal of a signal of the first node to a control terminal of the first switch;
• a delay circuit that delays the signal of the first node, outputs a delayed signal to an input node of the first CMOS inverter, and outputs an isolated outputs spike signal to an output terminal;
• and
• an intermediate node provided in the inverting circuit and coupled to an input terminal to which an input signal is input.

A spike generation circuit comprising:

• a first CMOS inverter connected between a first power supply and a second power supply, an output node of the first CMOS inverter being coupled to a first node that is an intermediate node coupled to an input terminal to which an input signal is input;
• a capacitance element having a first end coupled to the first node and a second end coupled to a reference potential terminal, an electric charge by the input signal being accumulated in the capacitance element;
• and
• a delay circuit that includes an even number of second CMOS inverters connected in an even number of stages between the first node and an output terminal, an input node of each of the even number of second CMOS inverters being coupled to the first node, an output node of each of the even number of second CMOS inverters being coupled to the output terminal, the delay circuit outputting an isolated output spike signal to the output terminal by outputting a signal to reset a charge accumulated in the capacitance element to an input node of the first CMOS inverter to cause a voltage of the first node to fall when the voltage of the first node becomes a predetermined value,
• wherein the even number of second CMOS inverters are six or more even number of second CMOS inverters.

A spike generation circuit comprising:

• a first CMOS inverter connected between a first power supply and a second power supply, an output node of the first CMOS inverter being coupled to a first node that is an intermediate node coupled to an input terminal to which an input signal is input;
• a capacitance element having a first end coupled to the first node and a second end coupled to a reference potential terminal, an electric charge by the input signal being accumulated in the capacitance element;
• a delay circuit that includes an even number of second CMOS inverters connected in an even number of stages between the first node and an output terminal, an input node of each of the even number of second CMOS inverters being coupled to the first node, an output node of each of the even number of second CMOS inverters being coupled to the output terminal, the delay circuit outputting an isolated output spike signal to the output terminal by outputting a signal to reset a charge accumulated in the capacitance element to an input node of the first CMOS inverter to cause a voltage of the first node to fall when the voltage of the first node becomes a predetermined value;
• and
• a switch that is connected in series with the first CMOS inverter between the first power supply and the second power supply and includes a control terminal to which a signal of an output node of an odd-numbered second CMOS inverter from the first node among the even number of second CMOS inverters is input.

A spike generation circuit comprising:

• a time constant circuit that includes a capacitor, which has a first end coupled to an output node and a second end coupled to a first reference potential terminal, and a constant current element or constant current circuit, which has a first end coupled to an input terminal to which an input signal of which a voltage depends on time is input and a second end coupled to the output node and generates a constant current corresponding to a voltage difference between the first end and the second end, the time constant circuit increasing a time constant of a rise of the input signal, and outputting a resulting signal to an intermediate node from the output node;
• and
• an output circuit that outputs an isolated output spike signal to an output terminal and resets a voltage of the intermediate node in response to the voltage of the intermediate node becoming a threshold voltage,
• wherein the output circuit outputs the isolated output spike signal after a delay time relating to a time constant of the time constant circuit after the input signal is input, and
• wherein the constant current element or constant current circuit includes a diode connected in a backward direction or a transistor having a control terminal to which a voltage is applied so that the transistor is in an on-state.

A spike generation circuit comprising:

• a time constant circuit that includes a capacitor, which has a first end coupled to an output node and a second end coupled to a first reference potential terminal, and a constant current circuit, which has a first end coupled to an input terminal to which an input signal of which a voltage depends on time is input and a second end coupled to the output node and generates a constant current corresponding to a voltage difference between the first end and the second end, the time constant circuit increasing a time constant of a rise of the input signal, and outputting a resulting signal to an intermediate node from the output node;
• and
• an output circuit that outputs an isolated output spike signal to an output terminal and resets a voltage of the intermediate node in response to the voltage of the intermediate node becoming a threshold voltage,
• wherein the constant current circuit is a current mirror circuit including:
• a first transistor having a current input terminal and a current output terminal, one of the current input terminal and the current output terminal being coupled to the input terminal, the other of the current input terminal and the current output terminal being coupled to the output node, and
• a second transistor having a current input terminal, a current output terminal, and a control terminal, one of the current input terminal and the current output terminal being coupled to the input terminal through a first diode connected in a forward direction, the other of the current input terminal and the current output terminal being coupled to a second reference potential terminal through a second diode connected in a backward direction, the control terminal being coupled to a control terminal of the first transistor.

A spike generation circuit comprising:

• a capacitor having a first end coupled to an intermediate node and a second end coupled to a first reference potential terminal;
• a voltage conversion circuit that includes a first element and a second element connected in series between an input terminal, to which an input signal of which a voltage depends on time is input, and a second reference potential terminal, and a resistance element having a first end coupled to a node, which is between the first element and the second element, and a second end coupled to the intermediate node, and outputs, to the intermediate node, a signal obtained by dividing a voltage of the input signal by the first element and the second element;
• and
• an output circuit that outputs an isolated output spike signal to an output terminal and resets a voltage of the intermediate node in response to the voltage of the intermediate node becoming a threshold voltage,
• wherein a product of a resistance value of the resistance element and a capacitance value of the capacitor is greater than a width of the isolated output spike signal.