Manufacturing method of a semiconductor structure

A manufacturing method of a semiconductor structure comprising:

• providing a substrate;
• forming a first metal layer on the substrate and patterning the first metal layer to define a gate line and a masking metal pattern, and the gate line is electrically connected to a gate;
• forming a gate insulating layer on the substrate and covering the gate line and the masking metal pattern;
• forming an oxide semiconductor material layer on the gate insulating layer;
• performing an annealing treatment to the oxide semiconductor material layer;
• forming an etch stopping material layer on the oxide semiconductor material layer;
• forming a photoresist material layer on the etch stopping material layer;
• defining the photoresist material layer with a half tone photomask to form a photoresist pattern;
• using the photoresist pattern as a mask, patterning the etch stopping material layer, to form an etch stopping pattern;
• using the photoresist pattern as the mask, patterning the oxide semiconductor material layer, to form an oxide semiconductor layer and to define a first opening overlapping the gate insulating layer;
• performing an ashing procedure to remove the photoresist pattern;
• using the etch stopping pattern as the mask, patterning the gate insulating layer, to form a first contacting window overlapping the masking metal pattern, wherein an orthographic projection of the first contacting window on the substrate is located within an orthographic projection of the first opening on the substrate;
• forming a second metal layer on the etch stopping pattern and patterning the second metal layer to define a source electrode, a drain electrode, a signal line and a data line, wherein parts of the etch stopping pattern are located between the second metal layer and the oxide semiconductor layer, and the data line is electrically connected to the masking metal pattern through the first contacting window;
• and
• patterning the oxide semiconductor layer to define an oxide semiconductor pattern, wherein the source electrode, the drain electrode and the signal line are electrically connected to the oxide semiconductor pattern.