Semiconductor device and method of forming the same

A method of forming a semiconductor device, comprising:

• forming a semiconductor stack on a substrate, wherein the semiconductor stack comprises a plurality of first layers and a plurality of second layers stacked alternately;
• patterning the semiconductor stack and the substrate to form a plurality of trenches in the substrate and a stack of semiconductor strips between the plurality of trenches;
• forming a dummy gate stack across the at least one stack of semiconductor strips;
• removing a portion of the stack of semiconductor strips at opposite sides of the dummy gate stack to form source/drain (S/D) recesses exposing the substrate;
• laterally recessing the plurality of first layers to form a plurality of cavities;
• forming a plurality of inner spacers in the plurality of cavities respectively after laterally recessing the plurality of first layers;
• forming a liner layer to cover the S/D recesses and the plurality of cavities, wherein the liner layer continuously vertically extends between adjacent second layers to conformally fill in the plurality of cavities and completely cover outer sidewalls of the plurality of inner spacers;
• and
• epitaxially growing S/D regions from the liner layer, wherein the S/D regions have a plurality of protrusions respectively filling into the plurality of cavities, and the plurality of protrusions are vertically sandwiched between the plurality of second layers.

A semiconductor device, comprising:

• a substrate comprising at least one fin;
• a plurality of semiconductor nanosheets stacked on the at least one fin;
• a source/drain (S/D) region abutting the plurality of semiconductor nanosheets;
• a gate stack wrapping the plurality of semiconductor nanosheets, wherein the gate stack comprises a gate dielectric layer and a gate electrode on the gate dielectric layer, wherein the gate dielectric layer between the plurality of semiconductor nanosheets has an outer sidewall concave from a sidewall of the plurality of semiconductor nanosheet to form a plurality of cavities between the plurality of semiconductor nanosheets;
• and
• a liner layer lining a bottom surface and a sidewall of the S/D region and sandwiched between the S/D region and the gate stack, wherein the liner layer continuously vertically extends between adjacent semiconductor nanosheets to conformally fill in the plurality of cavities and completely cover the outer sidewall of the gate dielectric layer, wherein the liner layer is in direct contact with the gate dielectric layer between the plurality of semiconductor nanosheets.