Source/drain formation with reduced selective loss defects

A structure comprising:

• an n-type Fin Field-Effect (FinFET) region and a p-type FinFET region;
• an n-type FinFET in the n-type FinFET region, wherein the n-type FinFET comprises:
• a first semiconductor fin;
• a first gate stack on the first semiconductor fin;
• and
• an n-type source/drain region aside the first gate stack;
• a first dielectric fin in the n-type FinFET region, wherein the first dielectric fin has a first width;
• a p-type FinFET in the p-type FinFET region, wherein the p-type FinFET comprises:
• a second semiconductor fin;
• a second gate stack on the second semiconductor fin;
• and
• a p-type source/drain region aside the second gate stack;
• and
• a second dielectric fin in the p-type FinFET region, wherein the second dielectric fin has a second width smaller than the first width.

A structure comprising:

• a semiconductor substrate;
• a plurality of isolation regions extending into the semiconductor substrate;
• a first n-type source/drain region and a second n-type source/drain region extending higher than top surfaces of the plurality of isolation regions;
• a first dielectric fin between the first n-type source/drain region and the second n-type source/drain region, wherein the first dielectric fin has a first width measured at a first level higher than the top surfaces of the plurality of isolation regions, and a second width measured at a second level lower than the top surfaces of the plurality of isolation regions;
• a first p-type source/drain region and a second p-type source/drain region extending higher than the top surfaces of the plurality of isolation regions;
• and
• a second dielectric fin between the first p-type source/drain region and the second p-type source/drain region, wherein the second dielectric fin has a third width measured at the first level, and a fourth width measured at the second level, and wherein the first width is greater than the third width.