Isolation structures in multi-gate semiconductor devices and methods of fabricating the same

A method, comprising:

• forming a semiconductor substrate, including:
• providing a first semiconductor layer, wherein the first semiconductor layer includes elemental Si;
• forming a second semiconductor layer on the first semiconductor layer, wherein the second semiconductor layer includes SiGe;
• forming a third semiconductor layer on the second semiconductor layer, thereby forming the semiconductor substrate, wherein the third semiconductor layer includes elemental Si;
• performing an implantation process to dope the second semiconductor layer with oxygen;
• and
• performing an annealing process to the doped second semiconductor layer to form an oxide layer;
• forming a multi-layer structure (ML) including alternating Si layers and SiGe layers over the semiconductor substrate;
• forming a placeholder gate stack over the ML;
• forming a source/drain (S/D) recess in the ML, thereby exposing the oxide layer;
• forming an S/D feature in the S/D recess;
• and
• forming a metal gate stack in place of the placeholder gate stack and in place of the SiGe layers of the ML.

A semiconductor structure, comprising:

• a semiconductor substrate;
• an oxide layer disposed over the semiconductor substrate, wherein the oxide layer includes germanium;
• a stack of semiconductor layers disposed over the oxide layer;
• a high-k metal gate structure (HKMG) interleaved with the stack of semiconductor layers;
• and
• an epitaxial source/drain (S/D) feature disposed adjacent to the HKMG, wherein a bottom portion of the epitaxial S/D feature is defined by the oxide layer.