Inner spacer liner

A semiconductor structure, comprising:

• a first epitaxial feature and a second epitaxial feature;
• a plurality of nanostructures extending between the first epitaxial feature and the second epitaxial feature along a first direction;
• a plurality of inner spacer features interleaving the plurality of nanostructures;
• a gate structure wrapping around each of the plurality of nanostructures;
• and
• a silicon liner sandwiched directly between the gate structure and each of the plurality of inner spacer features along the first direction,
• wherein the silicon liner is in contact with the first epitaxial feature and the second epitaxial feature.

A method, comprising:

• forming a stack over a substrate, wherein the stack comprises a plurality of silicon layers interleaved by a plurality of silicon germanium layers;
• forming a fin-shaped structure from the stack and the substrate, the fin-shaped structure comprising a channel region and a source/drain region;
• recessing the source/drain region to form a source/drain trench that exposes sidewalls of the plurality of silicon layers and the plurality of silicon germanium layers;
• selectively and partially recessing the plurality of silicon germanium layers to form a plurality of inner spacer recesses;
• depositing a semiconductor layer over the plurality of inner spacer recesses;
• depositing an inner spacer layer over the semiconductor layer;
• etching back the semiconductor layer and the inner spacer layer to form a plurality of inner spacer features in the plurality of inner spacer recesses;
• after the etching back, forming a source/drain feature in the source/drain trench;
• releasing the plurality of silicon layers in the channel region as a plurality of channel members;
• and
• forming a gate structure around each of the plurality of channel members.