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US 11,444,176 B2Granted
Structure and formation method of semiconductor device structure
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsPo-Chi Wu, Chai-Wei Chang, Kuo-Hui Chang, Yi-Cheng Chao
Life of this patent
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Abstract
Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a gate stack over a semiconductor substrate and a cap element over the gate stack. The cap element has an upper portion and a lower portion, and the upper portion is wider than the lower portion. The semiconductor device structure also includes a spacer element over a sidewall of the cap element and a sidewall of the gate stack.
Claims20
A semiconductor device, comprising:
- a gate stack over a semiconductor substrate, the gate stack comprising a work function layer and a conductive fill layer, the work function layer extending along sidewalls and a bottommost surface of the conductive fill layer, a topmost surface of the conductive fill layer being above a topmost surface of the work function layer, the sidewalls of the conductive fill layer extending from the bottommost surface of the conductive fill layer to the topmost surface of the conductive fill layer, an entirety of each of the sidewalls of the conductive fill layer being a planar sidewall;
- a cap element over the gate stack, a dielectric material of the cap element being in physical contact with the topmost surface of the conductive fill layer, the cap element having a first width near the gate stack and a second width near an upper portion of the cap element, the second width being greater than the first width, a portion of the conductive fill layer extending above a bottommost surface of the cap element;
- a spacer element extending along a sidewall of the cap element and a sidewall of the gate stack, the spacer element having an inner sidewall closest to the sidewall of the gate stack, the inner sidewall having a lower portion with a first uniform slope and an upper portion with a second uniform slope, the second uniform slope being less than the first uniform slope, the upper portion of the inner sidewall extending from the lower portion of the inner sidewall to a topmost surface of the spacer element, an interface between the lower portion and the upper portion being above the topmost surface of the conductive fill layer, wherein the gate stack further comprises a gate dielectric layer, a first portion of the gate dielectric layer being interposed between the work function layer and the semiconductor substrate, a second portion of the gate dielectric layer being interposed between the work function layer and the spacer element, the topmost surface of the conductive fill layer being above a topmost surface of the gate dielectric layer, the topmost surface of the gate dielectric layer being level with the topmost surface of the work function layer;
- and
- a source/drain region extending into the semiconductor substrate, a top surface of the source/drain region being above a bottom surface of the spacer element.
2 more elements
A semiconductor device, comprising:
- a gate stack over a semiconductor substrate, the gate stack comprising a work function layer and a conductive fill layer, the conductive fill layer being surrounded by the work function layer, a topmost surface of the conductive fill layer being above a topmost surface of the work function layer, the conductive fill layer having a sidewall extending from the topmost surface of the work function layer to the topmost surface of the conductive fill layer, an entirety of the sidewall of the conductive fill layer being a planar sidewall, wherein the gate stack further comprises a gate dielectric layer, the gate dielectric layer surrounding the work function layer, a topmost surface of the gate dielectric layer being level with the topmost surface of the work function layer;
- a cap element over the gate stack, a portion of the cap element extending below the topmost surface of the conductive fill layer, the portion of the cap element comprising a dielectric material, a sidewall of the cap element having a lower portion with a first uniform slope and an upper portion with a second uniform slope, the second uniform slope being less than the first uniform slope, the upper portion of the sidewall of the cap element extending from the lower portion of the sidewall of the cap element to a topmost surface of the cap element;
- a spacer element having a first portion extending along a sidewall of the gate stack and a second portion extending along the sidewall of the cap element, the first portion of the spacer element having a first width, the second portion of the spacer element having a second width, the first width being greater than the second width;
- and
- a source/drain region extending into the semiconductor substrate, a top surface of the source/drain region being above a bottom surface of the work function layer.
2 more elements
A semiconductor device, comprising:
- a gate stack over a semiconductor substrate, the gate stack comprising a work function layer and a conductive fill layer, the work function layer extending along sidewalls and a bottommost surface of the conductive fill layer, a topmost surface of the conductive fill layer being above a topmost surface of the work function layer, the conductive fill layer having a uniform width as the conductive fill layer extends away from the topmost surface of the work function layer and toward the topmost surface of the conductive fill layer;
- a cap element over the gate stack, a dielectric material of the cap element being in physical contact with the topmost surface of the work function layer, a width of the cap element increasing as the cap element extends away from the topmost surface of the conductive fill layer and toward a topmost surface of the cap element;
- a spacer element on a sidewall of the cap element and a sidewall of the gate stack, the spacer element having an inner sidewall facing the sidewall of the gate stack and the sidewall of the cap element, the inner sidewall having a lower portion with a first uniform slope and an upper portion with a second uniform slope, the second uniform slope being less than the first uniform slope, the upper portion of the inner sidewall extending from the lower portion of the inner sidewall to a topmost surface of the spacer element, at least a portion of the lower portion being above the topmost surface of the conductive fill layer, wherein the gate stack further comprises a gate dielectric layer, a portion of the gate dielectric layer extending along the inner sidewall of the spacer element, the topmost surface of the conductive fill layer being above a topmost surface of the gate dielectric layer, the topmost surface of the gate dielectric layer being level with the topmost surface of the work function layer;
- and
- a source/drain region extending into the semiconductor substrate, a top surface of the source/drain region being above a top surface of the semiconductor substrate.
2 more elements
Dependencies are inferred from the claim text.