Semiconductor device with Fin end spacer dummy gate and method of manufacturing the same

A method of manufacturing a semiconductor device, comprising:

• forming a first fin and a second fin, the first and second fins extending in a first direction and the first and second fins being aligned along the first direction,
• forming a dummy oxide layer on an isolation insulating layer and the first and second fins;
• forming a first dummy gate layer over the first fin, a second dummy gate layer over an edge of the first fin but not over the second fin and a third dummy gate layer over the second fin but not over the first fin, the first to third dummy gate layers extending in a second direction crossing the first direction and arranged in parallel with each other in the first direction, and the second dummy gate layer being disposed between the first dummy gate layer and the third dummy gate layer along the second direction;
• forming sidewall spacer layers on the first and second dummy gate layers;
• etching source/drain regions of the first fin, which are not covered by the sidewall spacer layers, thereby forming source/drain spaces;
• forming source/drain epitaxial layers in the source/drain spaces;
• forming an interlayer dielectric layer over the source/drain epitaxial layers and the first and second dummy gate layers;
• removing the first dummy gate layer thereby forming a first gate space, and at least a part of the second dummy gate layer thereby forming a second gate space;
• and
• forming a metal gate structure in the first gate space and forming a spacer dummy gate layer in the second gate space by fully filling the second gate space with a dielectric material.

A method of manufacturing a semiconductor device, comprising:

• a forming a first fin and a second fin, the first and second fins extending in a first direction and the first and second fins being aligned along the first direction;
• forming a dummy oxide layer on an isolation insulating layer and the first and second fins;
• forming a first dummy gate layer over the first fin, a second dummy gate layer over an edge of the first fin but not over the second fin, a third dummy gate layer over the second fin, and a fourth dummy gate layer over an edge of the second fin but not over the first fin, the first to fourth dummy gate layers extending in a second direction crossing the first direction and arranged in parallel with each other in the first direction and arranged in an order of the first dummy gate layer, the second dummy gate layer, the fourth dummy gate layer and the third dummy gate layer in the first direction;
• forming sidewall spacer layers on the first, second, third and fourth dummy gate layers;
• forming an interlayer dielectric layer over the first, second, third and fourth dummy gate layers;
• removing the first dummy gate layer thereby forming a first gate space, at least a part of the second dummy gate layer thereby forming a second gate space, the third dummy gate layer thereby forming a third gate space, and at least a part of the fourth dummy gate layer thereby forming a fourth gate space;
• and
• forming a metal gate structure in the first gate space and third gate space, respectively, and forming a spacer dummy gate layer in the second gate space and the fourth gate space, respectively by fully filling the second and fourth gate spaces with a dielectric material.