Transistor device with a gate structure having recesses overlying an interface between isolation and device regions

A transistor device, comprising:

• a device region disposed in a semiconductor substrate and surrounded by an isolation structure;
• a gate structure disposed on the device region, the gate structure comprising a gate dielectric layer separating a gate electrode from the device region, wherein the gate structure comprises a pair of recess regions that respectively overly an interface region of the isolation structure and the device region, wherein the gate electrode forms an ‘H’ shape when viewed on a face of the gate structure;
• a sidewall spacer outlining the ‘H’ shape, extending from the isolation structure up to a top surface that is flush with a top surface of the gate structure;
• a pair of source/drain regions disposed in the device region on opposite sides of the gate structure and laterally spaced apart by a channel region, wherein the channel region has a channel length extending along a first direction from one of the source/drain regions to the other one of the source/drain regions, wherein the channel region has a channel width extending along a second direction perpendicular to the first direction from one of the recess regions to the other one of the recess regions;
• and
• a resistive protection layer disposed on the device region under the pair of recess regions, extending upwardly along a sidewall of the sidewall spacer, further extending laterally on the top surface of the sidewall spacer and a portion of the top surface of the gate structure adjoining the recess regions, and having a bottom surface that is laterally flush with a bottom surface of the sidewall spacer.

A transistor device, comprising:

• an isolation structure disposed in a semiconductor substrate, wherein the isolation structure demarcates a device region of the semiconductor substrate;
• a gate structure overlying the device region of the semiconductor substrate, wherein the gate structure has a pair of recess regions that respectively overly an interface region of the isolation structure and the device region;
• a pair of source/drain regions disposed in the device region of the semiconductor substrate;
• a sidewall spacer arranged around an outer perimeter of the gate structure, the sidewall spacer extending into the pair of recess regions from outermost sidewalls of the gate structure and having an upper surface that is flush with a top surface of the gate structure;
• and
• a resistive protection layer disposed along an upper surface of the device region within the pair of recess regions, extending upwards along a sidewall of the sidewall spacer, and further extending laterally along the upper surface of the sidewall spacer and the top surface of the gate structure.