Semiconductor memory device and semiconductor memory manufacturing apparatus
AssigneeSamsung Electronics Co., Ltd.
InventorJae hoon Kim
Life of this patent
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Abstract
A first memory device includes a first magnetoresistive cell having a plurality of deposition layers. A second memory device includes a second magnetoresistive cell having a plurality of deposition layers. Each of the plurality of deposition layers of the second magnetoresistive cell corresponds to one of the plurality of deposition layers of the first magnetoresistive cell. One of the plurality of deposition layers of the second magnetoresistive cell is thinner than a corresponding deposition layer of the plurality of deposition layers of the first magnetoresistive cell.
Claims20
A semiconductor memory manufacturing apparatus comprising:
- a wafer holder configured to support a semiconductor wafer;
- a sputtering target holder obliquely located above the wafer holder;
- and
- a shielding plate interposed between the sputtering target holder and the wafer holder,
- wherein the shielding plate includes a first exposure area and a second exposure area,
- wherein the first exposure area is larger than the second exposure area, and
- wherein the shielding plate is spaced apart from the sputtering target holder and is disposed closer to the wafer holder than the sputtering target holder.
A semiconductor memory manufacturing apparatus comprising:
- a wafer holder configured to support a semiconductor wafer including a first memory area and a second memory area;
- a sputtering target holder obliquely located above the wafer holder;
- and
- a shielding plate interposed between the sputtering target holder and the wafer holder,
- wherein the shielding plate includes a first exposure area located above the first memory area, and a second exposure area located above the second memory area,
- wherein the first exposure area is larger than the second exposure area,
- wherein a first memory device is located in the first memory area,
- wherein a second memory device is located in the second memory area, and
- wherein the shielding plate is spaced apart from the sputtering target holder and is disposed closer to the wafer holder than the sputtering target holder.
A semiconductor memory manufacturing apparatus comprising:
- a process chamber in which a sputtering process is performed;
- a wafer holder located inside the process chamber and configured to support and rotate a semiconductor wafer including a first memory area and a second memory area;
- a sputtering target obliquely located above the semiconductor wafer inside the process chamber so that sputtering particles are obliquely incident on an upper surface of the semiconductor wafer during the sputtering process;
- and
- a shielding plate fixed to an upper portion of the wafer holder, configured to rotate with the wafer holder, and including a plurality of first exposure areas and second exposure areas,
- wherein the first exposure areas are located on the first memory area, the second exposure areas are located on the second memory area, and each of the first exposure areas has an exposure area per unit area larger than that of each of the second exposure areas,
- wherein each of the first exposure areas includes a first exposure hole to vertically pass through an entire area thereof, and
- wherein each of the second exposure areas includes a plurality of second exposure holes to vertically pass therethrough.
Dependencies are inferred from the claim text.