Spacerless source contact layer replacement process and three-dimensional memory device formed by the process

A method of forming a three-dimensional memory device, comprising:

• forming in-process source-level material layers comprising, from bottom to top, a lower source-level dielectric etch-stop layer, a source-level sacrificial layer, and an upper source-level dielectric etch-stop layer over a substrate;
• forming an alternating stack of insulating layers and sacrificial material layers over the in-process source-level material layers;
• forming memory openings through the alternating stack and into the in-process source-level material layers;
• forming memory opening fill structures in the memory openings, wherein each of the memory opening fill structures comprises a respective vertical semiconductor channel and a respective memory film;
• forming backside openings through the alternating stack and into the in-process source-level material layers;
• forming a source cavity by removing the source-level sacrificial layer selective to materials of the alternating stack, the upper source-level dielectric etch-stop layer, and the lower source-level dielectric etch-stop layer through the backside openings without sidewall spacers being located on the alternating stack in the backside openings;
• forming a continuous source contact layer in the source cavity and in peripheral portions of the backside openings;
• removing portions of the continuous source contact layer overlying the first tapered surfaces by performing an isotropic etch process, wherein remaining portions of the continuous source contact layer comprise a source contact layer;
• and
• replacing the sacrificial material layers with electrically conductive layers through the backside openings.

A three-dimensional memory device, comprising:

• source-level material layers located over a substrate and comprising, from bottom to top, a lower source-level dielectric etch-stop layer, a source contact layer, and an upper source-level dielectric etch-stop layer;
• alternating stacks of insulating layers and electrically conductive layers located over the source-level material layers;
• backside trenches laterally extending along a first horizontal direction and vertically extending between the alternating stacks and through the upper source-level dielectric etch-stop layer, wherein segments of sidewalls of the backside trenches located on the upper source-level dielectric etch-stop layer are tapered at a first taper angle with respect to a vertical direction;
• memory openings vertically extending through the alternating stacks;
• and
• memory opening fill structures located in the memory openings and comprising a respective vertical semiconductor channel and a respective memory film, wherein the source contact layer laterally surrounds and contacts a bottom end portion of each of the vertical semiconductor channels;
• wherein the source contact layer comprises:
• planar portions located above a horizontal plane including a top surface of the lower source-level dielectric etch-stop layer;
• and
• rail portions that protrude downward below the horizontal plane including the top surface of the lower source-level dielectric etch-stop layer;
• and
• wherein each of the rail portions of the source contact layer underlies a respective one of the backside trenches, and is located entirely within an area defined by a periphery of the respective one of the backside trenches located within a horizontal plane including bottommost surfaces of the alternating stack.

A three-dimensional memory device, comprising:

• source-level material layers located over a substrate and comprising, from bottom to top, a lower source-level dielectric etch-stop layer, a source contact layer, and an upper source-level dielectric etch-stop layer;
• alternating stacks of insulating layers and electrically conductive layers located over the source-level material layers;
• backside trenches laterally extending along a first horizontal direction and vertically extending between the alternating stacks and through the upper source-level dielectric etch-stop layer, wherein segments of sidewalls of the backside trenches located on the upper source-level dielectric etch-stop layer are tapered at a first taper angle with respect to a vertical direction;
• memory openings vertically extending through the alternating stacks;
• and
• memory opening fill structures located in the memory openings and comprising a respective vertical semiconductor channel and a respective memory film, wherein the source contact layer laterally surrounds and contacts a bottom end portion of each of the vertical semiconductor channels;
• wherein the source contact layer comprises:
• planar portions located above a horizontal plane including a top surface of the lower source-level dielectric etch-stop layer;
• and
• rail portions that protrude downward below the horizontal plane including the top surface of the lower source-level dielectric etch-stop layer;
• and
• wherein sidewalls of the rail portions of the source contact layer have a second taper angle that is within a range from 70% to 130% of the first taper angle.

A three-dimensional memory device, comprising:

• source-level material layers located over a substrate and comprising, from bottom to top, a lower source-level dielectric etch-stop layer, a source contact layer, and an upper source-level dielectric etch-stop layer;
• alternating stacks of insulating layers and electrically conductive layers located over the source-level material layers;
• backside trenches laterally extending along a first horizontal direction and vertically extending between the alternating stacks and through the upper source-level dielectric etch-stop layer, wherein segments of sidewalls of the backside trenches located on the upper source-level dielectric etch-stop layer are tapered at a first taper angle with respect to a vertical direction;
• memory openings vertically extending through the alternating stacks;
• and
• memory opening fill structures located in the memory openings and comprising a respective vertical semiconductor channel and a respective memory film, wherein the source contact layer laterally surrounds and contacts a bottom end portion of each of the vertical semiconductor channels;
• wherein:
• the vertical semiconductor channels comprise a first doped semiconductor material having a doping of a first conductivity type;
• the source contact layer comprises a second doped semiconductor material having a doping of a second conductivity type that is the opposite of the first conductivity type;
• the memory films comprise outer sidewalls that contact the upper source-level dielectric etch-stop layer;
• and
• the three-dimensional memory device comprises dielectric cap structures embedded in the lower source-level dielectric etch-stop layer, contacting a bottom end of a respective one of the vertical semiconductor channels, and comprising a stack of dielectric materials having a same set of dielectric materials as each of the memory films.