Three-dimensional semiconductor memory device

A semiconductor memory device, comprising:

• a stack structure comprising a plurality of electrodes and a plurality of insulating layers that are alternately stacked on a substrate;
• and
• a vertical channel structure penetrating the stack structure,
• wherein the vertical channel structure comprises a semiconductor pattern and a vertical insulating layer between the semiconductor pattern and the plurality of electrodes, and
• wherein the vertical insulating layer comprises a charge storage layer, a filling insulating layer, and a tunnel insulating layer,
• wherein the filling insulating layer and the tunnel insulating layer are between the charge storage layer and the semiconductor pattern,
• wherein the vertical insulating layer has a cell region between the semiconductor pattern and each of the plurality of electrodes and a cell separation region between the semiconductor pattern and each of the plurality of insulating layers,
• wherein the filling insulating layer of the cell region has a first thickness in a first direction parallel to the substrate,
• wherein the filling insulating layer of the cell separation region has a second thickness in the first direction, the second thickness being greater than the first thickness, and
• wherein the filling insulating layer of the cell region overlaps a corresponding one of the plurality of electrodes in the first direction.

A semiconductor memory device, comprising:

• a stack structure comprising a plurality of electrodes and a plurality of insulating layers that are alternately stacked on a substrate;
• and
• a vertical channel structure penetrating the stack structure,
• wherein the vertical channel structure comprises a semiconductor pattern and a vertical insulating layer between the semiconductor pattern and the plurality of electrodes, and
• wherein the vertical insulating layer comprises a charge storage layer, a filling insulating layer, and a tunnel insulating layer,
• wherein the vertical insulating layer has a cell region between the semiconductor pattern and each of the plurality of electrodes and a cell separation region between the semiconductor pattern and each of the plurality of insulating layers,
• wherein a bottom surface of the cell separation region and a bottom surface of the insulating layer adjacent to the cell separation region are at substantially same levels, respectively,
• wherein a top surface of the cell separation region and a top surface of the insulating layer adjacent to the cell separation region are at substantially same levels, respectively,
• wherein the filling insulating layer of the cell separation region extends from the bottom surface of the cell separation region to the top surface of the cell separation region, and
• wherein the filling insulating layer of the cell region overlaps a corresponding one of the plurality of electrodes in a first direction parallel to the substrate.