Method of making memory cells, high voltage devices and logic devices on a substrate

A method of forming a semiconductor device, comprising:

• providing a substrate of semiconductor material that includes a first area, a second area and a third area;
• recessing an upper surface of the substrate in the first area and an upper surface of the substrate in the second area relative to an upper surface of the substrate in the third area;
• forming a first conductive layer disposed over and insulated from the upper surfaces in the first and second areas;
• forming a second conductive layer disposed over and insulated from the first conductive layer in the first and second areas, and disposed over and insulated from the upper surface in the third area;
• performing one or more etches to selectively remove portions of the first and second conductive layers in the first area, to entirely remove the first and second conductive layers from the second area, while maintaining the second conductive layer in the third area, wherein the one or more etches result in pairs of stack structures in the first area with each of the stack structures including a control gate of the second conductive layer disposed over and insulated from a floating gate of the first conductive layer;
• forming first source regions in the substrate each disposed between one of the pairs of stack structures;
• forming a third conductive layer disposed over and insulated from the upper surfaces of the substrate in the first and second areas;
• forming a protective layer over the third conductive layer in the first and second areas;
• after the forming of the protective layer, removing the second conductive layer from the third area;
• after the removing of the second conductive layer from the third area, forming blocks of conductive material disposed over and insulated from the upper surface in the third area;
• after the forming of the blocks of conductive material in the third area, etching portions of the protective layer and portions of the third conductive layer in the first and second areas to form a plurality of select gates of the third conductive layer each disposed adjacent to one of the stack structures and to form a plurality of HV gates of the third conductive layer each disposed over and insulated from the upper surface in the second area, wherein for each of the pairs of stack structures, an erase gate of the third conductive layer is disposed between the pair of stack structures, and over and insulated from one of the source regions;
• after the forming of the plurality of select gates and the plurality of HV gates:
• forming a semi-nonconformal layer of flowable material in the first, second and third areas,
• removing a portion of the semi-nonconformal layer of flowable material from the protective layer in the first area while maintaining the semi-nonconformal layer of flowable material in the second and third areas,
• thinning the protective layer in the first area, and
• removing remaining portions of semi-nonconformal layer of flowable material in the first area and the semi-nonconformal layer of flowable material in the second and third areas;
• forming first drain regions in the substrate each adjacent to one of the select gates;
• forming second source regions in the substrate each adjacent one of the HV gates;
• forming second drain regions in the substrate each adjacent one of the HV gates;
• forming third source regions in the substrate each adjacent one of the blocks of conductive material;
• forming third drain regions in the substrate each adjacent one of the blocks of conductive material;
• removing the thinned protective layer in the first area to expose the select gates and the erase gate;
• forming silicide on the select gates and the erase gates;
• and
• replacing each of the blocks of conductive material with a block of metal material.