Gate-all-around field effect transistors in integrated circuits

An integrated circuit (IC) structure, comprising:

• a logic standard cell including an n-type active region and a p-type active region oriented lengthwise along a first direction and spaced from each other along a second direction substantially perpendicular to the first direction,
• wherein the n-type active region includes a first plurality of vertically stacked channel layers having a width W1 measured along the second direction, and
• wherein the p-type active region includes a second plurality of vertically stacked channel layers having a width W2 measured along the second direction, the width W1 being greater than the width W2;
• and
• a metal gate structure oriented lengthwise along the second direction, wherein the metal gate structure engages with the first plurality of vertically stacked channel layers to form a p-type device and with the second plurality of vertically stacked channel layers to form an n-type device.

An integrated circuit (IC) structure, comprising:

• a memory cell that includes a first p-type fin, a first n-type fin, a second n-type fin, and a second p-type fin disposed lengthwise along a first direction and spaced from each other in said order along a second direction substantially perpendicular to the first direction,
• wherein each of the first and the second p-type fins includes a first plurality of vertically stacked channel layers having a width W1 measured along the second direction,
• wherein each of the first and the second n-type fins includes a second plurality of vertically stacked channel layers having a width W2 measured along the second direction, the width W2 being less than the width W1, and
• wherein each of the first p-type fin, the first n-type fin, the second n-type fin, and the second p-type fin is continuous across a boundary of the memory cell;
• a standard logic cell that includes a third n-type fin and a third p-type fin oriented lengthwise along the first direction and spaced from each other along the second direction,
• wherein the third n-type fin includes a third plurality of vertically stacked channel layers having a width W3 measured along the second direction, and
• wherein the third p-type fin includes a fourth plurality of vertically stacked channel layers having a width W4 measured along the second direction, the width W3 being greater than or equal to the width W4;
• and
• a plurality of metal gate structures disposed over the first, the second, and the third n-type fins to form p-type devices and over the first, the second, and the third p-type fins to form n-type devices.