Back to results
US 11,444,085 B2Granted
Multi-layer thyristor random access memory with silicon-germanium bases
AssigneeTC Lab, Inc.
InventorHarry Luan
Life of this patent
Estimating the term…
Abstract
A semiconductor structure for a DRAM is described having multiple layers of arrays of thyristor memory cells with silicon-germanium base regions. Memory cells in a vertical string extending through the layers have an electrical connection to one terminal of the memory cells in that string. Word lines couple the strings together. Each layer of the array also includes bit line connections to memory cells on that layer. Select transistors enable the use of folded bit lines. Methods of fabricating the array are described.
Claims10
A semiconductor fabrication process comprising:
- depositing alternating layers of insulating material and first material on a semiconductor substrate;
- etching trenches through the alternating layers;
- removing the first material by laterally etching it from between the layers of insulating material to form cavities between the layers of insulating material;
- introducing a silicon containing gas and first conductivity type impurity into the process to thereby form one of a cathode or an anode for semiconductor devices in the cavities;
- introducing semiconductor material having an energy bandgap less than of silicon together with first and opposite conductivity type impurities to thereby form interior regions between the cathode and anode for the semiconductor devices;
- introducing a silicon containing gas and opposite conductivity type impurity into the process to thereby form the other of a cathode or an anode for the semiconductor devices in the cavities;
- and
- providing electrical connections to the semiconductor devices in the cavities.
5 more elements
Dependencies are inferred from the claim text.