Back to results
US 11,444,084 B2Granted
Multi-layer horizontal thyristor random access memory and peripheral circuitry
AssigneeTC Lab, Inc.
InventorHarry Luan
Life of this patent
Estimating the term…
Abstract
A semiconductor structure for a DRAM is described having multiple layers of arrays of thyristor memory cells and associated peripheral circuitry. Memory cells in a vertical string extending through the layers have an electrical connection to one terminal of the memory cells in that string. Word lines couple the strings together. Each layer of the array also includes bit line connections to memory cells on that layer. Methods of fabricating the array are described.
Claims6
A multi-layer electronic device comprising:
- a semiconductor substrate;
- z layers of semiconductor devices, each of the z layers including an array of x rows by y columns of semiconductor devices;
- a first set of electrical connections connecting strings of semiconductor devices, each string including one semiconductor device from each of the z layers in the array connected together;
- an array of x by y first electrical connections connecting a first terminal of each thyristor in each string to the semiconductor devices above it and the semiconductor device below it in that string;
- a first set of word line connections extending in parallel to connect rows of the strings together;
- a first set of bit line connections extending in parallel on each layer to connect together columns of semiconductor devices on each layer, the first set of bit line connections on each layer extending outward on each layer away from the array further than the second set of electrical connections on the layer immediately above it so as to form a stair-step arrangement of electrical connections;
- and
- peripheral circuitry connected to the first set of electrical connections, the first set of word line connections, and the first set of bit line connections for providing control signals to the first set of electrical connections, the first set of word line connections, and the first set of bit line connections.
5 more elements
A semiconductor fabrication process comprising:
- depositing a stack of alternating layers of insulating material and first material on a first portion of a semiconductor substrate;
- depositing dielectric material on a second portion of the semiconductor substrate;
- etching trenches through the stack of alternating layers, and in the same process, etching away the dielectric material from a peripheral circuit region of the second portion at a level coplanar with predetermined layers of the stack of alternating layers of insulating material and first material on the first portion;
- providing epitaxial semiconductor material on the peripheral circuit region and in selected locations over the first portion of the semiconductor substrate;
- removing selected regions of the epitaxial semiconductor material from the peripheral circuit region and filling those selected regions with dielectric to thereby define electrically isolated pockets for semiconductor devices;
- and
- forming semiconductor devices in the electrically isolated pockets.
4 more elements
Dependencies are inferred from the claim text.