Integrated circuit (IC) device

An integrated circuit device comprising:

• a fin-type active area protruding from a substrate and extending in a first horizontal direction;
• a pair of source/drain regions disposed on the fin-type active area;
• a nanosheet stack structure facing an upper surface of the fin-type active area with a first separation space between the nanosheet stack structure and the upper surface, the nanosheet stack structure comprising a plurality of nanosheets of which widths in the first horizontal direction are defined by the pair of source/drain regions;
• a gate line extending on the fin-type active area in a second horizontal direction intersecting the first horizontal direction and having a sub-gate portion disposed within a second separation space between the plurality of nanosheets;
• a gate dielectric layer interposed between the plurality of nanosheets and the gate line;
• and
• a bottom insulation structure filling the first separation space,
• wherein a vertical thickness of a first nanosheet closest to the fin-type active area from among the plurality of nanosheets is less than a vertical thickness of a second nanosheet from among the plurality of nanosheets, the second nanosheet disposed above the first nanosheet.

An integrated circuit device comprising:

• a fin-type active area extending on a substrate in a first horizontal direction;
• a source/drain region disposed on the fin-type active area;
• a nanosheet stack structure disposed on the fin-type active area, the nanosheet stack structure comprising a first nanosheet closest to the fin-type active area and a second nanosheet disposed above the first nanosheet;
• a gate line covering the nanosheet stack structure on the fin-type active area, and extending in a second horizontal direction intersecting the first horizontal direction;
• a gate dielectric layer disposed between the nanosheet stack structure and the gate line;
• and
• a bottom insulation structure interposed between the fin-type active area and the first nanosheet, and integrally connected to the gate dielectric layer,
• wherein a thickness of the first nanosheet in a vertical direction is less than a thickness of the second nanosheet in the vertical direction.