Semiconductor packages
AssigneeSamsung Electronics Co., Ltd.
InventorsYongjin Park, Jiin Yu, Jin-San Jung
Life of this patent
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Abstract
A semiconductor package may include a first semiconductor chip, a second semiconductor chip on the first semiconductor chip, and an adhesive layer between the first semiconductor chip and the second semiconductor chip. The first semiconductor chip may include a semiconductor substrate and a plurality of protection layers on the semiconductor substrate. The topmost layer of the protection layers may have a top surface with convex portions and concave portions, and the convex portions and the concave portions may be in contact with the adhesive layer.
Claims20
A semiconductor package comprising:
- a first semiconductor chip adhered to a second semiconductor chip by an adhesive layer between the first semiconductor chip and the second semiconductor chip, wherein:
- the first semiconductor chip comprises:
- a semiconductor substrate;
- and
- a first protection layer and a second protection layer sequentially stacked on the semiconductor substrate,
- the first protection layer includes a plurality of holes defined therein, and
- the second protection layer is in contact with the adhesive layer.
A semiconductor package comprising:
- a first semiconductor chip;
- a second semiconductor chip on the first semiconductor chip;
- and
- an adhesive layer between the first semiconductor chip and the second semiconductor chip, wherein:
- the first semiconductor chip comprises:
- a semiconductor substrate;
- and
- a plurality of protection layers on the semiconductor substrate,
- a topmost layer among the protection layers has a top surface with convex portions and concave portions, and
- the convex portions and the concave portions are in contact with the adhesive layer.
A semiconductor package comprising:
- a first semiconductor chip;
- a second semiconductor chip stacked on the first semiconductor chip;
- and
- an adhesive layer between the first semiconductor chip and the second semiconductor, wherein:
- the first semiconductor chip comprises:
- a semiconductor substrate;
- a through-via penetrating the semiconductor substrate;
- a first protection layer and a second protection layer, which are sequentially stacked on the semiconductor substrate;
- and
- an upper pad disposed on the second protection layer and connected to the through-via,
- the first protection layer is provided to define a plurality of holes, and
- a level of a bottom surface of the second protection layer is lower than a level of a top surface of the first protection layer, in a region overlapped with the holes.
Dependencies are inferred from the claim text.