3D semiconductor package including memory array

A device comprising:

• a logic die comprising a semiconductor substrate;
• an interconnect structure over the logic die;
• and
• a memory array over the interconnect structure, the memory array comprising:
• a first memory cell comprising a first portion of a gate dielectric layer contacting a first word line;
• and
• a second memory cell comprising a second portion of the gate dielectric layer contacting a second word line, wherein the second memory cell is disposed further from the interconnect structure than the first memory cell in a first direction perpendicular to a major surface of the semiconductor substrate, wherein the second word line has a length in a second direction perpendicular to the first direction greater than a length of the first word line in the second direction, and wherein the logic die comprises circuits configured to perform read and write operations in the memory array.

A method comprising:

• forming a memory array, forming the memory array comprising:
• forming a multi-layer stack over a substrate, the multi-layer stack comprising alternating conductive layers and dielectric layers;
• patterning a first trench extending through the multi-layer stack;
• depositing a gate dielectric layer along sidewalls and a bottom surface of the first trench, wherein the gate dielectric layer is deposited in contact with a first sidewall of a first conductive layer of the conductive layers;
• depositing an oxide semiconductor (OS) layer over the gate dielectric layer;
• forming a first interconnect structure over the memory array;
• and
• bonding an integrated circuit device to the first interconnect structure using dielectric-to-dielectric bonding and metal-to-metal bonding.