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US 11,444,067 B2Granted
Stacked interposer structures, microelectronic device assemblies including same, and methods of fabrication, and related electronic systems
AssigneeMicron Technology, Inc.
InventorsOwen R. Fay, Chan H. Yoo
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Abstract
An interposer comprises a semiconductor material and includes cache memory under a location on the interposer for a host device. Memory interface circuitry may also be located under one or more locations on the interposer for memory devices. Microelectronic device assemblies incorporating such an interposer and comprising a host device and multiple memory devices are also disclosed, as are methods of fabricating such microelectronic device assemblies.
Claims18
A stacked interposer structure, consisting of:
- a first interposer comprising:
- a first core comprising a semiconductor material;
- a first redistribution structure comprising multiple redistribution layers (RDLs) over a side of the first core, the first redistribution structure configured for operably coupling, on a surface of the first redistribution structure, to one or more memory device stack locations and to a processor device location;
- cache memory at least partially within the core adjacent the first redistribution structure under and operably coupled through the first redistribution structure to the processor device location;
- and
- a first set of through silicon vias (TSVs) extending from the first redistribution structure through the first core to an opposite side of the first core;
- and
- a second interposer comprising:
- a second core comprising a semiconductor material;
- a second redistribution structure comprising multiple redistribution layers (RDLs) over a side of the second core and facing in a direction opposite a direction of the first redistribution structure;
- a second set of through silicon vias (TSVs) extending from the second redistribution structure through the second core to an opposite side of the second core;
- and
- the first and second redistribution structures being operably coupled through both the first set of TSVs and the second set of TSVs.
10 more elements
A microelectronic device assembly, comprising:
- a stacked interposer structure consisting of two directly interconnected, superimposed interposers, each interposer having a semiconductor core and a redistribution structure on one side thereof;
- at least one host device and at least one memory device mounted on, and operably coupled to, a redistribution structure of one of the two interconnected interposers, the at least one host device operably coupled to cache memory at least partially within the semiconductor core of the one interposer under a location of the at least one host device through the redistribution structure of the one interposer;
- and
- circuitry of the stacked interposer structure operably coupling the at least one host device and the at least one memory device and extending to a side of the stacked interposer structure opposite the at least one host device and the at least one memory device for connection to higher level packaging.
1 more element
An electronic system, comprising:
- an input device and an output device, the electronic system further comprising:
- a processor device and at least one memory device operably coupled to a redistribution structure of an interposer comprising a semiconductor core including cache memory circuitry located under the processor device and operably coupled thereto through the redistribution structure of the interposer, the redistribution structure of the interposer operably coupled to another redistribution structure of another interposer at least by through silicon vias (TSVs) extending from the redistribution structure of the interposer through the semiconductor core to a side thereof opposite the redistribution structure;
- and
- the input device and the output device operably coupled to the processor through conductive paths of the another interposer.
1 more element
Dependencies are inferred from the claim text.