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US 11,444,062 B2Granted
Memory scaling semiconductor device
AssigneeSanDisk Technologies LLC
InventorNagesh Vodrahalli
Life of this patent
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Abstract
A semiconductor device is disclosed including a memory module formed from a pair of semiconductor dies mounted face to face to each other at the wafer level. These die pairs are formed using wafer-to-wafer bonding technology, where the wafers may be bonded to each other when they are of full thickness. Once bonded, respective inactive surfaces of the wafers may be thinned and then the die pairs diced from the wafers to form a completed memory module. When the wafers are bonded face to face, they compensate each other, mechanically resulting in the die pair having a minimum warpage.
Claims15
An integrated memory module comprising:
- a first semiconductor die, comprising:
- a first memory array formed in a face of the first semiconductor die, the face comprising a first surface, the first memory array having a first coefficient of thermal expansion,
- a first substrate next to the first memory array and having a second coefficient of thermal expansion,
- a first group of bond pads formed in the first surface of the first semiconductor die, and
- electrical interconnections connected to the first group of bond pads at the first surface;
- and
- a second semiconductor die, comprising:
- a second memory array formed in a face of the second semiconductor die, the face comprising a second surface, the second memory array having a third coefficient of thermal expansion,
- a second substrate next to the second memory array and having a fourth coefficient of thermal expansion, and
- a second group of bond pads formed in the face of the second semiconductor die, the first and second groups of bond pads bonded to each other;
- wherein the integrated memory module is configured to avoid warping by bonding the first and second semiconductor dies together face to face so that the first, second, third and fourth coefficients of thermal expansion balance each other out.
8 more elements
An integrated memory module comprising:
- a first semiconductor die, comprising:
- first and second opposed surfaces,
- a first memory array at the first surface,
- a first substrate at the second surface,
- a first set of bond pads at the second surface configured to electrically connect the integrated memory module to a host device;
- and
- a second semiconductor die, comprising:
- third and fourth opposed surfaces, the first surface of the first semiconductor die bonded to the third surface of the second semiconductor die,
- a second memory array at the third surface, and
- a second substrate at the fourth surface;
- wherein the electrical connections comprise:
- a first set of electrical connections electrically coupled to the first set of bond pads and the first memory array, the first set of electrical connections configured to allow access to the first memory array independently of the second memory array,
- a second set of electrical connections electrically coupled to the first set of bond pads and the second memory array, the second set of electrical connections configured to allow access to the second memory array independently of the first memory array, and
- a third set of electrical connections electrically coupled to the first set of bond pads and the first and second memory arrays, the third set of electrical connections configured to allow access to the first and second memory arrays together;
- and
- wherein the memory module is configured to be stacked in an overlapped configuration and packaged together with other memory modules that are electrically coupled to each other by the first, second, third and fourth sets of vias through the first and second semiconductor dies.
13 more elements
An integrated memory module comprising:
- a first semiconductor die, comprising:
- first and second opposed surfaces,
- a first memory array at the first surface,
- a first substrate at the second surface,
- a first set of bond pads at the second surface configured to electrically connect the integrated memory module to a host device, and
- electrical connections electrically coupled at least to the first set of bond pads;
- and
- a second semiconductor die, comprising:
- third and fourth opposed surfaces, the first surface of the first semiconductor die bonded to the third surface of the second semiconductor die,
- a second memory array at the third surface, and
- a second substrate at the fourth surface;
- wherein the electrical connections comprise:
- a first set of electrical connections electrically coupled to the first set of bond pads and the first memory array, the first set of electrical connections configured to allow access to the first memory array independently of the second memory array,
- a second set of electrical connections electrically coupled to the first set of bond pads and the second memory array, the second set of electrical connections configured to allow access to the second memory array independently of the first memory array, and
- a third set of electrical connections electrically coupled to the first set of bond pads and the first and second memory arrays, the third set of electrical connections configured to allow access to the first and second memory arrays together.
12 more elements
Dependencies are inferred from the claim text.