Semiconductor package

A semiconductor package according comprising:

• a lower package;
• and
• an upper package disposed on the lower package,
• wherein the lower package includes:
• a first semiconductor device including a first through electrode;
• a second semiconductor device disposed on the first semiconductor device and including a second through electrode electrically connected to the first through electrode;
• a first molding member covering a sidewall of at least one of the first semiconductor device and the second semiconductor device;
• a second molding member covering a sidewall of the first molding member;
• an upper redistribution layer disposed on the second semiconductor device and electrically connected to the second through electrode;
• a lower redistribution layer disposed below the first semiconductor device and electrically connected to the first through electrode;
• and
• an external connection terminal electrically connected to the lower redistribution layer,
• wherein the upper package includes:
• a third semiconductor device;
• and
• a first connection terminal electrically connected to the third semiconductor device and the upper redistribution layer, and
• wherein an upper surface of the second through electrode is coplanar with a lower surface of the upper redistribution layer.

A semiconductor package comprising:

• a first semiconductor device including a first through electrode;
• a second semiconductor device disposed on the first semiconductor device and including a second through electrode electrically connected to the first through electrode;
• a first molding member covering a sidewall of at least one of the first semiconductor device and the second semiconductor device, wherein the first molding member is spaced apart from all through electrodes;
• an upper redistribution layer disposed on the second semiconductor device and including an upper redistribution pattern electrically connected to the second through electrode;
• and
• a third semiconductor device disposed on the upper redistribution layer and electrically connected to the upper redistribution pattern.