Package structures and methods of forming

A semiconductor device comprising:

• a first redistribution structure comprising:
• a first insulating layer;
• and
• metallization layers over the first insulating layer, each of the metallization layers being separated by one or more insulating layers;
• through vias on the first redistribution structure, the through vias extending through an uppermost insulating layer of the first redistribution structure, a portion of the through vias extending over an uppermost surface of the uppermost insulating layer;
• a first integrated circuit die on the first redistribution structure, a front side of the first integrated circuit die comprising a first pad and a first die connector electrically connected to the first pad;
• a second integrated circuit die on the first redistribution structure, a front side of the second integrated circuit die comprising a second pad and a second die connector electrically connected to the second pad;
• encapsulant around the first integrated circuit die and second integrated circuit die;
• a second redistribution structure directly on the encapsulant, the through vias, the first integrated circuit die, and the second integrated circuit die, the front side of the first integrated circuit die facing the second redistribution structure, the front side of the second integrated circuit die facing the second redistribution structure;
• and
• a third integrated circuit die directly coupled to the second redistribution structure by first external electrical connectors mechanically attached to the second redistribution structure, an active side of the third integrated circuit die facing the second redistribution structure, wherein the third integrated circuit die overlaps the first integrated circuit die.

A semiconductor device comprising:

• a first redistribution structure comprising:
• a first insulating layer;
• a first metallization layer;
• a second metallization layer, wherein the first metallization layer is interposed between the second metallization layer and the first insulating layer;
• and
• a second insulating layer, wherein the second metallization layer is interposed between the second insulating layer and the first metallization layer;
• a through via on the first redistribution structure, a portion of the through via extending through the second insulating layer to the second metallization layer;
• a first integrated circuit die on the first redistribution structure;
• encapsulant around the first integrated circuit die and the through via, wherein a top surface of the through via, a top surface of the encapsulant, and the top surface of the first integrated circuit die are level;
• a second redistribution structure on the encapsulant, an active side of the first integrated circuit die facing the second redistribution structure;
• a second integrated circuit die directly attached to the second redistribution structure by a first external electrical connector, wherein the second integrated circuit die at least partially overlaps the first integrated circuit die;
• and
• a second external electrical connector extending through the first insulating layer.