Non-volatile memory with capacitors using metal under signal line or above a device capacitor

An apparatus, comprising:

• a semiconductor die, comprising:
• a substrate;
• a three dimensional non-volatile memory array formed above the substrate;
• a plurality of metal interconnect layers configured to route signals within the semiconductor die, the plurality of metal interconnect layers are positioned above the substrate, above the three dimensional non-volatile memory array and across a top area of the semiconductor die;
• electrical components, including a device capacitor, positioned in the semiconductor die on a top surface of the substrate and below the plurality of metal interconnect layers, the metal interconnect layers are electrically connected to the electrical components below the plurality of metal interconnect layers;
• an I/O pad;
• and
• multiple capacitors connected to the I/O pad, the multiple capacitors are positioned in the metal interconnect layers, at least one of the multiple capacitors is positioned directly above the device capacitor in the semiconductor die.