Semiconductor packages including an insulating layer including a recessed surface and methods of manufacturing the same

A semiconductor package comprising:

• a lower protective layer;
• a first conductive pattern on the lower protective layer;
• a first insulating layer on the lower protective layer and contacting a side surface of the first conductive pattern, wherein the side surface of the first conductive pattern extends between an upper surface and a lower surface of the first conductive pattern;
• a second insulating layer on the first insulating layer and the first conductive pattern;
• and
• a semiconductor chip on the second insulating layer,
• wherein the first insulating layer includes a first upper surface and an inclined surface adjacent to the side surface of the first conductive pattern,
• the first upper surface of the first insulating layer extends parallel to an upper surface of the lower protective layer,
• a distance from the upper surface of the lower protective layer to the first upper surface of the first insulating layer is equal to a distance from the upper surface of the lower protective layer to the upper surface of the first conductive pattern, and
• a distance from the upper surface of the lower protective layer to a first portion of the inclined surface of the first insulating layer is different from a distance from the upper surface of the lower protective layer to a second portion of the inclined surface of the first insulating layer,
• wherein the inclined surface of the first insulating layer is between the first conductive pattern and the first upper surface of the first insulating layer.

A semiconductor package comprising:

• a redistribution substrate;
• a semiconductor chip on the redistribution substrate;
• and
• a molding film on the redistribution substrate and on a side surface of the semiconductor chip,
• wherein the redistribution substrate includes:
• a lower protective layer;
• a first conductive pattern on the lower protective layer;
• a first insulating layer on the lower protective layer and surrounding the first conductive pattern;
• a second insulating layer on the first insulating layer and the first conductive pattern;
• and
• a terminal pad on the second insulating layer and electrically connected to the semiconductor chip, and
• wherein the first insulating layer includes an inclined surface, a first upper surface and a second upper surface,
• the first upper surface is between the inclined surface and the second upper surface and extends parallel to an upper surface of the lower protective layer,
• the second upper surface is coplanar with an upper surface of the first conductive pattern,
• the lower protective layer, the first insulating layer, and the second insulating layer are stacked in a first direction,
• a distance from the upper surface of the lower protective layer to the first upper surface in the first direction is shorter than a distance from the upper surface of the lower protective layer to the second upper surface in the first direction, and
• a distance from the upper surface of the lower protective layer to a first portion of the inclined surface in the first direction is different from a distance from the upper surface of the lower protective layer to a second portion of the inclined surface in the first direction.