Chip package structure with cavity in interposer

A method for forming a package structure, comprising:

• forming a cavity on a bottom surface of an interposer substrate, wherein the interposer substrate includes a silicon substrate;
• disposing a first semiconductor device in the cavity and on a bottom surface of the cavity;
• forming a second cavity on a top surface of a package substrate;
• stacking the interposer substrate with the first semiconductor device over the package substrate such that the bottom surface of the interposer substrate faces the top surface of the package substrate and the first semiconductor device is received in the second cavity;
• and
• disposing a second semiconductor device over the interposer substrate.

A package structure, comprising:

• a package substrate having a top surface and a first cavity formed on the top surface;
• an interposer substrate disposed over the package substrate, wherein the interposer substrate includes a silicon substrate, and has a bottom surface facing and adjacent to the top surface of the package substrate and a second cavity formed on the bottom surface;
• a first semiconductor device received in the second cavity and electrically connected to the interposer substrate via a plurality of first conductive joints, wherein the first semiconductor device also extends into the first cavity of the package substrate;
• and
• a second semiconductor device disposed on a top surface of the interposer substrate opposite the bottom surface.