Semiconductor structure and method of manufacture

A method comprising:

• etching openings in a dielectric layer over a substrate, the dielectric layer covering an active device on the substrate;
• depositing a conductive material in the openings;
• planarizing the conductive material with the dielectric layer to form a first test pad comprising a frame, a grid region within the frame, and a probe region within an interior of the grid region, the grid region comprising conductive grid features separated by portions of the dielectric layer, a bottom surface of the probe region extending below a top surface of the active device;
• depositing a second dielectric layer over the first test pad;
• and
• forming a second test pad in the second dielectric layer.

A method of manufacturing a semiconductor device, the method comprising:

• forming a first test pad within a dielectric material covering an active device, the first test pad comprising:
• an outer frame;
• a grid region extending inwards from the outer frame, the grid region comprising conductive grid members that are separated from one another by the dielectric material, a continuous first portion of the dielectric material being surrounded by conductive grid members in a plan view, wherein the continuous first portion has a length and a width in the plan view, the length being greater than the width;
• and
• a panel region within an interior of the grid region, a bottom surface of the panel region extending below a top surface of the active device, wherein a first one of the conductive grid members connects the panel region to the outer frame, and wherein the first one of the conductive grid members has a first thickness and the panel region has a second thickness, the first thickness being less than the second thickness.