Semiconductor devices with backside air gap dielectric

A method, comprising:

• providing a structure having a silicon substrate, an isolation structure over the silicon substrate, one or more semiconductor fins extending from the silicon substrate and over the isolation structure, one or more transistors formed over the one or more semiconductor fins, and an interconnect structure over the one or more transistors, wherein the silicon substrate is at a backside of the structure and the interconnect structure is at a frontside of the structure;
• attaching the frontside of the structure to a carrier substrate;
• thinning the structure from the backside of the structure until the isolation structure and the one or more semiconductor fins are exposed from the backside of the structure;
• etching two holes through the one or more semiconductor fins to expose two source/drain features of the one or more transistors from the backside of the structure;
• forming two metal plugs in the two holes respectively;
• etching the one or more semiconductor fins between the two metal plugs from the backside of the structure, thereby forming a trench;
• and
• forming a dielectric liner on sidewalls of the trench and over the isolation structure and the metal plugs, wherein the dielectric liner is thicker at an opening portion of the trench than at another portion of the trench that is deeper than the opening portion so that an air gap is formed inside the trench.

A method, comprising:

• providing a structure having a substrate, an isolation structure over the substrate, one or more semiconductor fins extending from the substrate and above the isolation structure, one or more transistors formed over the one or more semiconductor fins, wherein the substrate is at a backside of the structure and the one or more transistors are at a frontside of the structure;
• thinning the structure from the backside of the structure until the isolation structure and the one or more semiconductor fins are exposed from the backside of the structure;
• etching two holes through the one or more semiconductor fins to expose two source/drain features of the one or more transistors from the backside of the structure;
• forming two metal plugs in the two holes respectively;
• selectively etching the one or more semiconductor fins between the two metal plugs from the backside of the structure, thereby forming a trench;
• forming a dielectric liner on sidewalls of the trench and over the isolation structure and the metal plugs, wherein the dielectric liner is thicker at an opening portion of the trench than at another portion of the trench that is deeper than the opening portion;
• depositing a sacrificial dielectric layer covering the dielectric liner;
• and
• performing a chemical-mechanical planarization (CMP) process to remove the sacrificial dielectric layer and to recess the dielectric liner until the isolation structure and the metal plugs are exposed.