Method of fabricating semiconductor device with metal pad extending into top metal layer

A method of fabricating a semiconductor device, comprising:

• forming a first dielectric layer on a first conductive layer;
• forming a first opening in the first dielectric layer and the first conductive layer comprising:
• performing a main etching process on the first dielectric layer;
• and
• performing an over-etching process to remove a first thickness of the first conductive layer, wherein a ratio of the first thickness of the first conductive layer to an entire thickness of the first conductive layer is greater than ⅕;
• forming a second conductive layer on the first dielectric layer and filling into the first opening;
• patterning the second conductive layer, thereby forming a conductive pattern on the first dielectric layer and in the first opening,
• performing a first annealing process on the first dielectric layer and the first conductive layer having the first opening;
• forming a second dielectric layer over the first dielectric layer and the conductive pattern;
• forming a second opening in the second dielectric layer, wherein the second opening exposes the conductive pattern;
• and
• performing a second annealing process on the conductive pattern and the second dielectric layer having the second opening,
• wherein the first annealing process and the second annealing process are performed in different atmospheres.

A method of fabricating a semiconductor device, comprising:

• forming a first passivation layer on a top metal layer of an interconnect structure;
• patterning the first passivation layer comprising:
• performing a main etching process to form the first opening in the first passivation layer;
• and
• performing an over-etching process to form a recess in the top metal layer;
• performing a first annealing process on the first passivation layer having the first opening and the top metal layer having the recess;
• forming a barrier layer on a top surface of the first passivation layer and filling into the first opening in the first passivation layer and the recess in the top metal layer;
• forming a conductive layer on the barrier layer in the first opening and the recess;
• patterning the conductive layer, thereby forming a conductive pad on a first portion of the top surface of the first passivation layer and in the first opening and the recess, wherein a second portion of the top surface of the first passivation layer is exposed;
• forming a second passivation layer over the first passivation layer and the conductive pad;
• and
• patterning the second passivation layer to form a second opening, wherein the second opening exposes the conductive pad;
• and
• performing a second annealing process on the conductive pad and the second passivation layer having the second opening,
• wherein the first annealing process and the second annealing process are performed in different atmospheres.