Semiconductor ICF target processing

A process for manufacturing a plurality of individual spherical devices in parallel from a wafer of semiconductor material, comprising:

• creating a first wafer by:
• depositing one or more hard mask films upon a single-crystal n-type silicon substrate;
• applying a uniform coat of photoresist pattern on top of the one or more hard mask films, wherein the first wafer is rotating as the uniform coat of photoresist pattern is applied;
• etching through the one or more hard mask films with vias, wherein the vias range in diameter from 1 μm to 1 mm;
• forming hemispherical cavities using an isotropic dry etch of the n-type silicon substrate having one or more hard mask films, wherein the hemispherical cavities range in diameter from 100 μm to 5 cm;
• using a Chemical Mechanical Planarization (CMP) process to polish and remove one or more of the hard mask films;
• incorporating a p-type dopant on a surface of the hemispherical cavities;
• placing hollow silicon dioxide fuel spheres within the hemispherical cavity;
• and
• filling the hollow silicon dioxide fuel spheres with a fusion fuel mixture,
• creating a second wafer by repeating the above steps of creating a first wafer, wherein the second wafer has the same pattern of hemispherical cavities as the first wafer;
• mating the first and second wafers together;
• adhesively bonding the first and second wafers together;
• etching to selectively remove what remains from the single-crystal n-type silicon substrate to liberate a spherical device;
• and
• repeating all of the above steps that produce the plurality of individual spherical devices, in parallel.