Memory device and method for error detection

A memory device capable of detecting an error bit, comprising:

• a syndrome generating circuit, comprising a plurality of input terminals and a plurality of logic circuits;
• and
• a plurality of latch circuits, coupled to the syndrome generating circuit, configured to set the plurality of input terminals of the syndrome generating circuit to a predetermined logic state according to a pre-charge reset signal, and provide a plurality of data bits to the plurality of input terminals of the syndrome generating circuit after the plurality of input terminals of the syndrome generating circuit are set to the predetermined logic state,
• wherein the syndrome generating circuit is configured to generate a syndrome bit based on the plurality of data bits by the plurality of logic circuits, and the syndrome bit indicates a presence of an error bit among the plurality of data bits,
• wherein each of the plurality of latch circuits comprises an input terminal, a first logic circuit, a second logic circuit, a third logic circuit, a fourth logic circuit, and an output terminal,
• the input terminal of each of the plurality of latch circuits is coupled to receive one of the plurality of data bits,
• the output terminal of each of the plurality of latch circuits is coupled to one of the plurality of input terminals of the syndrome generating circuit,
• the first logic circuit is configured to perform a first logic operation to a signal on a node between the third logic circuit and the fourth logic circuit and the pre-charge reset signal to generate a first intermediate bit,
• the second logic circuit is coupled between the first logic circuit and the node, and is configured to be enabled to perform a second logic operation to the first intermediate bit to generate a second intermediate bit when an inverse latch clock signal is in a high logic state,
• the third logic circuit is coupled between the input terminal and the node, and is configured to be enabled to perform a third logic operation to one of the plurality of data bits for outputting a third intermediate bit to the node when a latch clock signal is in the high logic state, and
• the fourth logic circuit is coupled between the node and the output terminal, and is configured to perform a fourth logic operation to the signal on the node to set the plurality of input terminals of the syndrome generating circuit to the predetermined logic state and to provide one of the plurality of data bits to one of the plurality of input terminals of the syndrome generating circuit.