Failure mode analysis method for memory device

A failure mode analysis method for a memory device, comprising:

• scanning a wafer by a test system to generate a failure pattern of the wafer, and obtaining a failure count of a plurality of bits in the wafer by a test program,
• defining a grouping table of the plurality of bits according to a word-line layout, a bit-line layout, and an active area layout;
• grouping the plurality of bits into a core group and a gap group according to at least one process in a self-aligned double patterning process, wherein the core group has a first plurality of bits and the gap group has a second plurality of bits different from the first plurality of bits;
• and
• respectively counting a failure count of the first plurality of bits in the core group and a failure count of the second plurality in the gap group to generate a core failure data and a gap failure data.