Memory device including test control circuit

A memory device comprising:

• a memory cell array suitable for storing data;
• an input/output circuit suitable for inputting and outputting the data stored in the memory cell array;
• a test register circuit suitable for testing the input/output circuit;
• a data generation circuit suitable for generating pattern data and random data during a test operation;
• a selection circuit suitable for selectively outputting the pattern data and the random data to the test register circuit and the memory cell array during the test operation;
• and
• a replica circuit having a replica configuration of the test register circuit by modeling the test register circuit, and suitable for generating operation data based on output data of the data generation circuit,
• wherein the replica circuit is capable of testing the test register circuit based on a comparison of data outputted from the test register circuit with data outputted from the replica circuit.

A stacked memory device comprising:

• a base die;
• and
• a core die stacked on the base die,
• wherein the base die comprises:
• an interface circuit suitable for transmitting and receiving signals to and from a controller;
• a test register circuit suitable for testing the interface circuit;
• and
• a test control block comprising a replica circuit having a replica configuration of the rest register circuit by modeling the test register circuit, and suitable for generating pattern data and random data to selectively test the test register circuit and the core die during a test operation.