Method and circuit for scan dump of latch array

A scannable memory circuit on an integrated circuit having a scan chain, comprising:

• a row counter that increments once every N clock periods, dependent upon a scan enable signal, and resets after reaching a value of M, where both M and N are positive integers greater than 1;
• an input buffer including N buffer latches enabled to load data during a first part of a clock of the clock periods;
• an input selector having N outputs respectively coupled to N inputs of the N buffer latches of the input buffer, the input selector having N first inputs coupled to a first functional data path and N second inputs coupled to a feedback data path, the input selector configured to select between the N first inputs and the N second inputs based on the scan enable signal;
• a clocking circuit, coupled to an output of the row counter and having a functional write address input and M row clock outputs, the clocking circuit configured to drive a selected row clock output of the M row clock outputs to an active state during a second part of the clock period, a selection of the selected row clock output based on the output of the row counter dependent upon the scan enable signal, or the functional write address input dependent on a write enable signal;
• an array of M rows and N columns of storage elements, inputs of each storage element of a column of the N columns of storage elements coupled to an output of a corresponding buffer latch of the N buffer latches of the input buffer, each storage element of a row of the M rows of storage elements coupled to a respective row clock output of the M row clock outputs and enabled to load during an active state of the respective row clock output;
• an output selector, coupled to the output of the row counter and having a functional read address input, M sets of N inputs respectively coupled to outputs of storage elements of the array of M rows and N columns of storage elements, and N outputs coupled to a second functional data path, the output selector configured to select between the M sets of N inputs based on the functional read address input or the output of the row counter dependent upon the scan enable signal;
• a scan input for the scan chain coupled to a first line of the feedback data path, other lines of the feedback data path respectively coupled to different outputs of the N outputs of the output selector, wherein a particular output of the N outputs of the output selector is not coupled to the feedback data path;
• and
• a scan output of the scan chain coupled to the particular output of the N outputs of the output selector.