Memory device architecture coupled to a System-on-Chip
AssigneeMicron Technology, Inc.
InventorsAntonino Mondello, Alberto Troia
Life of this patent
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Abstract
The present disclosure relates to an apparatus comprising a non-volatile memory architecture configured to be coupled to a System-on-Chip (SoC) device. The non-volatile memory device coupled to the SoC having a structurally independent structure linked to the SoC includes a plurality of sub arrays forming a matrix of memory cells with associated decoding and sensing circuitry, sense amplifiers coupled to a corresponding sub array, a data buffer comprising a plurality of JTAG cells coupled to outputs of the sense amplifiers; and a scan-chain connecting together the JTAG cells of the data buffer.
Claims20
An apparatus, comprising:
- a System on Chip (SoC);
- and
- a non-volatile memory device coupled to the SoC and having a structurally independent structure linked to the SoC, the non-volatile memory device comprising:
- a plurality of sub arrays forming a matrix of memory cells with associated decoding and sensing circuitry;
- sense amplifiers coupled to a corresponding sub array;
- a data buffer comprising a plurality of JTAG cells coupled to outputs of the sense amplifiers, wherein each JTAG cell of the plurality of JTAG cells include:
- a parallel input (PIN) terminal and a serial input (SIN) terminal;
- and
- a parallel output terminal (POUT) and a serial output terminal (SOUT);
- and
- a scan-chain connecting together the JTAG cells of the data buffer, wherein the scan-chain includes;
- the PIN terminal of a first JTAG cell coupled to an output of a first sense amplifier;
- the POUT terminal of the first JTAG cell is coupled to a corresponding data input/output terminal of the SoC;
- the SIN terminal of the first JTAG cell is coupled to the SOUT terminal of a second JTAG cell;
- and
- the SOUT terminal of the first JTAG cell is coupled to the SIN terminal of a third JTAG cell.
A non-volatile memory architecture configured to be coupled to a System-on-Chip (SoC) device, comprising:
- an array of memory cells formed by plurality of sub arrays;
- sense amplifiers coupled to a corresponding sub array of the plurality of sub- arrays;
- sense amplifiers coupled to the memory cells having respective outputs;
- a data buffer including a plurality of JTAG cells coupled to the outputs of the sense amplifiers, wherein each JTAG cell of the plurality of JTAG cells include;
- a parallel input (PIN) terminal and a serial input (SIN) terminal;
- and
- a parallel output terminal (POUT) and a serial output terminal (SOUT);
- and
- a scan-chain connecting together the JTAG cells of the data buffer, wherein the scan-chain includes;
- the PIN terminal of a first JTAG cell is coupled to an output of a first sense amplifier;
- the POUT terminal of the first JTAG cell is coupled to a corresponding data input/output terminal of the SoC;
- the SIN terminal of the first JTAG cell is coupled to SOUT terminal of a second JTAG cell;
- and
- the SOUT terminal of the first JTAG cell is coupled to the SIN terminal of a third JTAG cell.
An integrated circuit, comprising:
- a System on Chip (SoC) device;
- and
- a non-volatile memory device coupled to the SoC, wherein the SoC and the non-volatile memory device are independent dies and are coupled via pins or pads, or both;
- and wherein:
- a memory array in the memory device including a plurality of independently addressable sub arrays;
- sense amplifiers coupled to corresponding outputs of the sub arrays and coupled to a communication channel of the SoC device;
- and
- a scan-chain comprising modified JTAG cells, wherein the scan-chain include a parallel input (PIN) terminal of a first JTAG cell coupled to an output of a first sense amplifier, a parallel output terminal (POUT) of the first JTAG cell coupled to a corresponding data input/output terminal of the SoC, a serial input (SIN) terminal of the first JTAG cell coupled to the serial output terminal (SOUT) of a second JTAG cell, and a serial output terminal (SOUT) of the first JTAG cell is coupled to a serial input (SIN) terminal of a third JTAG cell.
Dependencies are inferred from the claim text.