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US 11,443,820 B2Granted
Memory device, memory address decoder, system, and related method for memory attack detection
AssigneeMicrochip Technology Incorporated
InventorsLorenzo Bedarida, Simone Bartoli, Albert S. Weiner
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Abstract
A memory device, memory address decoder, a memory system and related method for memory attack detection are disclosed. An apparatus includes a memory decoder include multiple stages in a decoding path configured to generate a select signal from an input address signal, and fault detecting logic operably coupled with the memory decoder and configured to receive feedback signals distributed from the multiple stages indicative of a fault along the decoding path.
Claims18
An apparatus, comprising:
- a memory address decoder including multiple stages in a decoding path to generate a select signal from an input address signal, wherein each of at least two stages of the multiple stages includes respective integrated fault detection circuitry to:
- detect an erred bit along a respective decoding path of the at least two stages;
- and
- generate a feedback signal indicative of the detected erred bit, and
- fault detecting logic operably coupled with the memory address decoder to receive the respective feedback signals distributed from the multiple stages indicative of a fault along the decoding path, the received feedback signals including feedback signals generated by the respective integrated fault detection circuitry of the at least two stages of the multiple stages.
2 more elements
A method, the method comprising:
- decoding an input signal via a memory address decoder including multiple stages in a decoding path to generate a select signal from an input address signal;
- performing fault detecting within at least two stages of the multiple stages in the decoding path;
- detecting erred bits along a respective decoding path of the at least two stages at least partially responsive to the fault detecting;
- generating feedback signals indicative of the detected erred bits, the feedback signals distributed within the multiple stages;
- and
- receiving, at fault detecting logic, feedback signals indicative of a fault along the decoding path, the received feedback signals comprising the generated feedback signals distributed within the multiple stages.
3 more elements
Dependencies are inferred from the claim text.