Memory structure with marker bit and operation method thereof

A memory structure with marker bit, comprising:

• a memory array, having a plurality of blocks, each of the plurality of blocks having a plurality of word lines coupled to memory cells;
• at least one marker bit column having at least one marker bit unit used as a marker bit, and the at least one marker bit unit being coupled to at least one of the plurality of word lines;
• and
• a controller performing controls on the memory array,
• wherein in performing a program operation to the memory array, for each of the plurality of blocks, the controller pre-reads data from the at least one marker bit unit, and programs the at least one marker bit unit and performs the program operation to the memory array if the data is a first digital value that indicates an erase state;
• and
• in performing a block erase operation to the blocks of the memory array, for each of the plurality of blocks, the controller pre-reads the data from the at least one marker bit unit and erases the at least one marker bit unit during performing the block erase operation to the blocks of the memory array if the data is a second digital value that indicates a program state, and the controller skips the block erase operation if the data is the first digital value.