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US 11,443,801 B2Granted
Semiconductor memory apparatus for preventing disturbance
AssigneeSK hynix Inc.
InventorJin Su Park
Life of this patent
Estimating the term…
Abstract
A semiconductor memory apparatus includes an access line control circuit. The access line control circuit applies a selected bias voltage to a selected access line coupled with a target memory cell and applies a first unselected bias voltage to an unselected access line adjacent to the selected access line. A second unselected bias voltage is applied to an unselected access line not adjacent to the selected access line.
Claims12
A semiconductor memory apparatus comprising:
- a plurality of global word lines;
- a plurality of word line groups each including a plurality of word lines coupled with the plurality of global word lines, respectively;
- and
- a word line control circuit configured to select one of the plurality of word line groups based on a word line select signal and configured to apply at least two of a selected word line bias voltage, a first unselected word line bias voltage, a second unselected word line bias voltage, and a third unselected word line bias voltage to the plurality of global word lines,
- wherein the first to third unselected word line voltages have higher voltage level than the selected word line voltage.
2 more elements
A semiconductor memory apparatus comprising:
- a word line control circuit configured to apply a selected word line bias voltage to a selected word line coupled with the target memory cell and configured to apply a word line voltage, having a voltage level between a first unselected word line bias voltage and a second unselected word line bias voltage, which is lower in proportion to a distance from the selected word line to an unselected word line to which the word line voltage is applied.
Dependencies are inferred from the claim text.