Back to results
US 11,443,800 B2Granted
Semiconductor memory apparatus for preventing disturbance
AssigneeSK hynix Inc.
InventorJin Su Park
Life of this patent
Estimating the term…
Abstract
A semiconductor memory apparatus includes an access line control circuit. The access line control circuit applies a selected bias voltage to a selected access line coupled with a target memory cell and applies a first unselected bias voltage to an unselected access line adjacent to the selected access line. A second unselected bias voltage is applied to an unselected access line not adjacent to the selected access line.
Claims12
A semiconductor memory apparatus comprising:
- a plurality of global bit lines;
- a plurality of bit line groups each including a plurality of bit lines coupled with the plurality of global bit lines, respectively;
- and
- a bit line control circuit configured to select one of the plurality of bit line groups based on a bit line select signal and configured to apply at least two of a selected bit line bias voltage, a first unselected bit line bias voltage, a second unselected bit line bias voltage, and a third unselected bit line bias voltage to the plurality of global bit lines.
1 more element
A semiconductor memory apparatus comprising:
- a bit line control circuit configured to apply a selected bit line bias voltage to a selected bit line coupled with a target memory cell and configured to apply a bit line voltage, having a voltage level between a first unselected bit line bias voltage and a second unselected bit line bias voltage, which is higher in proportion to a distance from the selected bit line to an unselected bit line to which the bit line voltage is applied.
Dependencies are inferred from the claim text.