Memory device and electronic device
AssigneeSemiconductor Energy Laboratory Co., Ltd.
InventorsTakahiko Ishizu, Toshihiko Saito, Hideki Uochi, Shunpei Yamazaki
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AssigneeSemiconductor Energy Laboratory Co., Ltd.
InventorsTakahiko Ishizu, Toshihiko Saito, Hideki Uochi, Shunpei Yamazaki
Estimating the term…
A novel memory device is provided. The memory device includes a plurality of memory cells, and one memory cell includes a first transistor and a second transistor. One of a source and a drain of the first transistor is electrically connected to a gate of the second transistor through a node SN. Data written through the first transistor is retained at the node SN. When an OS transistor is used as the first transistor, formation of a storage capacitor is not needed. A region with a low dielectric constant is provided outside the memory cell, whereby noise from the outside is reduced and stable operation is achieved.
A memory device comprising:
A memory device comprising:
Dependencies are inferred from the claim text.