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US 11,443,795 B2Granted
SRAM with address dependent power usage
AssigneeAmbiq Micro, Inc.
InventorChristophe J. Chevallier
Life of this patent
Estimating the term…
Abstract
A SRAM system having an address scheme and/or wire control layout. By preferentially accessing a defined address range mapped to SRAM array blocks located near a controller, significant power savings can be realized. In one embodiment, the address scheme determines a range physically closer to a central control location. In another embodiment, the wire control layout reduces number and length of active wires, further reducing power consumption.
Claims23
A SRAM circuit comprising:
- arrays of SRAM bit cells, each capable of storing a bit of information, that together define an address bitmap, each array of the arrays of SRAM bit cells including a sense amplifier and a write driver;
- peripheral circuitry able to generate selected control, data, and address signals, connected to the arrays of SRAM bit cells and positioned at a designated location, the peripheral circuitry including at least one array decoder for each array of the arrays of SRAM bit cells located at the designated location and signal lines coupling the at least one array decoder to the sense amplifier and the write driver of the each array, the sense amplifier and the write driver of each array of the arrays of SRAM bit cells not being at the designated location and being adjacent the arrays of SRAM bit cells;
- and
- wherein a subset of arrays in the arrays of SRAM bit cells are mapped to a subset of the address bitmap, and are placed adjacent to the designated location.
1 more element
An array control circuit connected to a plurality of array blocks comprising:
- peripheral circuitry connected by signal lines to the plurality of array blocks to access a subset of array blocks during an operation, the peripheral circuitry being positioned at a designated location, with an array decoder for each block of the plurality of array blocks being located at the designated location and sense amplifiers and write drivers for each block of the plurality of array blocks not being locate at the designated location;
- and
- wherein only those signal lines connecting the peripheral circuitry to the accessed subset of array blocks are active during the operation.
A system with multiple arrays that can be selectively accessed, comprising:
- first circuitry positioned adjacent to at least some of the multiple arrays, the multiple arrays accessible and controllable with one or more control signals, and with only circuitry connected to accessed arrays being enabled, wherein the first circuitry is sense amplifiers and write drivers;
- and
- second circuitry generating at least some of the one or more control signals to enable the first circuitry, the second circuitry being at a designated location at a center of the multiple arrays and including array decoders for the multiple arrays, the first circuitry not being at the designated location;
- wherein the multiple arrays and the second circuitry are in different power domains.
1 more element
Dependencies are inferred from the claim text.