Battery life based on inhibited memory refreshes
AssigneeIntel Corporation
InventorsRamkumar Jayaraman, Krishnaprasad H, Kausik Ghosh
Life of this patent
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Abstract
Disclosed herein are mechanisms and methods for reducing power consumed by various DRAM technologies (e.g., high-capacity DRAM and/or 3D DRAM) which may impact battery life of the platform. These mechanisms and methods may opportunistically reduce the power consumed by DRAM by inhibiting periodic refresh commands to memory ranks that are not in-use. Since these mechanisms and methods may be based on enhancements to memory controllers, they may accordingly be operating system (OS) agnostic.
Claims18
An apparatus comprising:
- a processor;
- and
- a memory controller coupled to the processor, wherein the memory controller is to:
- identify a command provided to a memory interface;
- set, based on an identification that the command targets a first range of memory and an identification that the command is of a type for which memory refreshes are employed, a stored value of a register to a predetermined value;
- determine, based on the stored value of the register being the predetermined value, that the first range of memory is to remain active;
- and
- allow, based on the stored value of the register being the predetermined value, the first range of memory to refresh.
A machine-readable storage media having one or more machine-readable instructions stored thereon that, when executed, cause one or more machines to perform a method comprising:
- identifying a command provided to a memory interface;
- setting, based on an identification that the command targets a first range of memory and an identification that the command is of a type for which memory refreshes are employed, a stored value of a register to a predetermined value;
- determining, based on the stored value of the register being the predetermined value, that the first range of memory that is to remain active;
- and
- allowing, based on the stored value of the register being the predetermined value, the first range of memory to refresh.
A system comprising:
- a processor;
- a memory controller coupled to the processor;
- a Dynamic Random Access Memory (DRAM) Dual In-Line Memory Module (DIMM) coupled to the memory controller via a memory interface;
- a wireless interface to allow the processor to communicate with another device, wherein the memory controller is to:
- identify a command provided to the memory interface;
- set, based on an identification that the command targets a first range of memory and an identification that the command is of a type for which memory refreshes are employed, a stored value of a register to a predetermined value;
- determine, based on the stored value of the register being the predetermined value, that the first range of memory is to remain active;
- and
- allow, based on the stored value of the register being the predetermined value, the first range of memory to refresh, wherein the first range is a rank of memory on the DRAM DIMM.
Dependencies are inferred from the claim text.